Integrated circuit device with improved layout

An integrated circuit (IC) device, comprising:

• a plurality of cells at respective cell locations, each cell of the plurality of cells comprising:
• a device layer comprising a plurality of gates spaced in a first direction in accordance with a gate pitch;
• a first plurality of metal lines in a first metal layer overlying the device layer;
• a second plurality of metal lines in a second metal layer overlying the first metal layer and spaced in the first direction in accordance with a metal line pitch;
• and
• a connection pin comprising a first metal line of the first plurality of metal lines coupled to the device layer and to a first metal line of the second plurality of metal lines, wherein
• a ratio of the metal line pitch to the gate pitch is less than 1 and is represented as X:Y, where X and Y are integer values,
• first and second cells of the plurality of cells correspond to a same IC component and have a same cell width between first and second lateral edges in the first direction,
• the first cell of the plurality of cells comprises the first metal line of the second plurality of metal lines of the corresponding connection pin a first distance from the first lateral edge,
• the second cell of the plurality of cells comprises the first metal line of the second plurality of metal lines of the corresponding connection pin a second distance from the first lateral edge, and the first and second distances differ by a fraction of the metal line pitch equal to 1/X.

An integrated circuit (IC) device, comprising:

• a plurality of cells at respective cell locations, each cell of the plurality of cells comprising:
• a device layer comprising a plurality of gates spaced in a first direction in accordance with a gate pitch;
• a first plurality of metal lines in a first metal layer overlying the device layer;
• a second plurality of metal lines in a second metal layer overlying the first metal layer and spaced in the first direction in accordance with a metal line pitch;
• an input pin comprising a first metal line of the first plurality of metal lines coupled through a via to a first metal line of the second plurality of metal lines;
• and
• a contact electrically connected to the first metal line of the first plurality of metal lines and to a gate of the plurality of gates,
• wherein
• a ratio of the metal line pitch to the gate pitch is less than 1,
• first and second cells of the plurality of cells correspond to a same IC component and have a same cell width between first and second lateral edges in the first direction,
• the first cell of the plurality of cells comprises the first metal line of the second plurality of metal lines of the corresponding input pin a first distance from the first lateral edge,
• the second cell of the plurality of cells comprises the first metal line of the second plurality of metal lines of the corresponding input pin a second distance from the first lateral edge, and
• the first and second distances differ by a fraction of the metal line pitch.