US 9,799,575 B2Granted

Integrated circuit containing DOEs of NCEM-enabled fill cells

AssigneePDF Solutions, Inc.

InventorsStephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama

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Abstract

Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

Claims11

Dependent claims

An integrated circuit (IC), comprising at least:

a standard cell area that includes a mix of at least one thousand logic cells and fill cells of different widths and uniform heights, placed into at least twenty adjacent rows, with at least twenty cells placed side-by-side in each row;
wherein said integrated circuit includes at least a first Design of Experiments (DOE), said first DOE comprising a plurality of similarly-configured, non-contact electrical measurement (NCEM)-enabled fill cells, wherein each NCEM-enabled fill cell comprises at least:
first and second elongated conductive supply rails, formed in a connector or interconnect stack layer, extending across the entire width of said cell, and configured for compatibility with corresponding supply rails contained in the logic cells of said standard cell region;
a NCEM pad, formed in a conductive layer, said NCEM pad being at least two times larger, in at least one dimension, than a minimum size permitted by design rules;
a rectangular test area defined by selected boundaries of at least first and second distinct, mask-patterned features, said test area being characterized by two dimensional parameters;
a first conductive pathway that electrically connects the first mask-patterned feature to said NCEM pad;
and,
a second conductive pathway that electrically connects the second mask-patterned feature to a permanently or virtually grounded structure;
wherein each of the similarly-configured, NCEM-enabled fill cells in the first DOE is configured to render a first selected manufacturing failure observable as an abnormal pad-to-ground leakage, conductance, or resistance, detected by voltage contrast (VC) inspection of the NCEM pad;
and,
wherein the similarly-configured, NCEM-enabled fill cells of the first DOE include a plurality of variants, where the variants differ in terms of their respective probability of presenting an abnormal pad-to-ground leakage, conductance, or resistance as a result of said first selected manufacturing failure.

8 more elements

An integrated circuit (IC), comprising at least:

a standard cell area that includes a mix of at least one thousand logic cells and fill cells of different widths and uniform heights, placed into at least twenty adjacent rows, with at least twenty cells placed side-by-side in each row;
wherein said integrated circuit includes at least a first Design of Experiments (DOE), said first DOE comprising a plurality of similarly-configured, NCEM-enabled fill cells, wherein each NCEM-enabled fill cell comprises at least:
first and second elongated conductive supply rails, formed in a connector or interconnect stack layer, extending across the entire width of said cell, and configured for compatibility with corresponding supply rails contained in the logic cells of said standard cell region;
a NCEM pad, formed in one or more conductive layer(s), said NCEM pad being at least two times larger, in at least one dimension, than the minimum size permitted by design rules;
a rectangular test area defined by selected boundaries of a plurality of mask-patterned features, said test area characterized by two dimensional parameters, said plurality of mask-patterned features including at least first and second features that are electrically connected in the absence of a first manufacturing failure;
a first conductive pathway that electrically connects the first mask-patterned feature to said NCEM pad;
and,
a second conductive pathway that electrically connects the second mask-patterned feature to a permanently or virtually grounded structure;
wherein each of the similarly-configured NCEM-enabled fill cells in the first DOE is configured to render a first selected manufacturing failure observable as an abnormally high pad-to-ground conductance or leakage, detected by VC inspection of the NCEM pad;
wherein the similarly-configured NCEM-enabled fill cells of the first DOE include a plurality of variants, where the variants differ in terms of their respective probability of presenting an abnormally high pad-to-ground conductance or leakage as a result of said first selected manufacturing failure;
and,
wherein the similarly-configured NCEM-enabled fill cells of the first DOE are selected from the list consisting of:
source/drain (AA)-tip-to-tip-short-configured, NCEM-enabled fill cells;
source/drain contact (AACNT)-tip-to-tip-short-configured, NCEM-enabled fill cells;
AACNT-AA-tip-to-tip-short-configured, NCEM-enabled fill cells;
source/drain silicide (TS)-tip-to-tip-short-configured, NCEM-enabled fill cells;
gate (GATE)-tip-to-tip-short-configured, NCEM-enabled fill cells;
gate contact (GATECNT)-GATE-tip-to-tip-short-configured, NCEM-enabled fill cells;
GATECNT-tip-to-tip-short-configured, NCEM-enabled fill cells;
GATECNT-AACNT-tip-to-tip-short-configured, NCEM-enabled fill cells;
first wiring layer (M1)-tip-to-tip-short-configured, NCEM-enabled fill cells;
via to interconnect stack (V0)-tip-to-tip-short-configured, NCEM-enabled fill cells;
M1-V0-tip-to-tip-short-configured, NCEM-enabled fill cells;
first interconnect via (V1)-M1-tip-to-tip-short-configured, NCEM-enabled fill cells;
V1-tip-to-tip-short-configured, NCEM-enabled fill cells;
second wiring layer (M2)-tip-to-tip-short-configured, NCEM-enabled fill cells;
M2-V1-tip-to-tip-short-configured, NCEM-enabled fill cells;
second interconnect via (V2)-M2-tip-to-tip-short-configured, NCEM-enabled fill cells;
third wiring layer (M3)-tip-to-tip-short-configured, NCEM-enabled fill cells;
V2-tip-to-tip-short-configured, NCEM-enabled fill cells;
M3-V2-tip-to-tip-short-configured, NCEM-enabled fill cells;
AA-tip-to-side-short-configured, NCEM-enabled fill cells;
AACNT-tip-to-side-short-configured, NCEM-enabled fill cells;
AACNT-AA-tip-to-side-short-configured, NCEM-enabled fill cells;
GATE-AA-tip-to-side-short-configured, NCEM-enabled fill cells;
GATECNT-GATE-tip-to-side-short-configured, NCEM-enabled fill cells;
GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells;
TS-GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells;
GATECNT-AACNT-tip-to-side-short-configured, NCEM-enabled fill cells;
M1-tip-to-side-short-configured, NCEM-enabled fill cells;
V0-tip-to-side-short-configured, NCEM-enabled fill cells;
M1-V0-tip-to-side-short-configured, NCEM-enabled fill cells;
V1-M1-tip-to-side-short-configured, NCEM-enabled fill cells;
V1-tip-to-side-short-configured, NCEM-enabled fill cells;
M2-tip-to-side-short-configured, NCEM-enabled fill cells;
M2-V1-tip-to-side-short-configured, NCEM-enabled fill cells;
V2-M2-tip-to-side-short-configured, NCEM-enabled fill cells;
M3-tip-to-side-short-configured, NCEM-enabled fill cells;
V2-tip-to-side-short-configured, NCEM-enabled fill cells;
M3-V2-tip-to-side-short-configured, NCEM-enabled fill cells;
AA-side-to-side-short-configured, NCEM-enabled fill cells;
AACNT-side-to-side-short-configured, NCEM-enabled fill cells;
AACNT-AA-side-to-side-short-configured, NCEM-enabled fill cells;
AACNT-GATE-side-to-side-short-configured, NCEM-enabled fill cells;
GATE-side-to-side-short-configured, NCEM-enabled fill cells;
GATECNT-GATE-side-to-side-short-configured, NCEM-enabled fill cells;
TS-GATE-side-to-side-short-configured, NCEM-enabled fill cells;
GATECNT-side-to-side-short-configured, NCEM-enabled fill cells;
GATECNT-AACNT-side-to-side-short-configured, NCEM-enabled fill cells;
M1-side-to-side-short-configured, NCEM-enabled fill cells;
V0-side-to-side-short-configured, NCEM-enabled fill cells;
M1-V0-side-to-side-short-configured, NCEM-enabled fill cells;
V1-M1-side-to-side-short-configured, NCEM-enabled fill cells;
V1-side-to-side-short-configured, NCEM-enabled fill cells;
M2-side-to-side-short-configured, NCEM-enabled fill cells;
M2-V1-side-to-side-short-configured, NCEM-enabled fill cells;
V2-M2-side-to-side-short-configured, NCEM-enabled fill cells;
M3-side-to-side-short-configured, NCEM-enabled fill cells;
V2-side-to-side-short-configured, NCEM-enabled fill cells;
M3-V2-side-to-side-short-configured, NCEM-enabled fill cells;
AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
AACNT-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
GATE-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
GATE-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
GATECNT-GATE-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
GATECNT-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
GATECNT-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
GATECNT-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
V0-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
V0-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
V0-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
V0-GATE-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
V0-GATECNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
M1-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
M1-GATECNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
M1-V0-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
V1-M1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
V1-V0-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
M2-M1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
M2-V1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
V2-V1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
V2-M2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
M3-M2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
M3-V2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;
AA-diagonal-short-configured, NCEM-enabled fill cells;
TS-diagonal-short-configured, NCEM-enabled fill cells;
AACNT-diagonal-short-configured, NCEM-enabled fill cells;
AACNT-AA-diagonal-short-configured, NCEM-enabled fill cells;
GATE-diagonal-short-configured, NCEM-enabled fill cells;
GATE-AACNT-diagonal-short-configured, NCEM-enabled fill cells;
GATECNT-GATE-diagonal-short-configured, NCEM-enabled fill cells;
GATECNT-diagonal-short-configured, NCEM-enabled fill cells;
GATECNT-AACNT-diagonal-short-configured, NCEM-enabled fill cells;
M1-diagonal-short-configured, NCEM-enabled fill cells;
V0-diagonal-short-configured, NCEM-enabled fill cells;
M1-V0-diagonal-short-configured, NCEM-enabled fill cells;
V1-M1-diagonal-short-configured, NCEM-enabled fill cells;
V1-diagonal-short-configured, NCEM-enabled fill cells;
M2-diagonal-short-configured, NCEM-enabled fill cells;
M2-V1-diagonal-short-configured, NCEM-enabled fill cells;
M3-diagonal-short-configured, NCEM-enabled fill cells;
V2-M2-diagonal-short-configured, NCEM-enabled fill cells;
V2-diagonal-short-configured, NCEM-enabled fill cells;
M3-V2-diagonal-short-configured, NCEM-enabled fill cells;
AA-corner-short-configured, NCEM-enabled fill cells;
AACNT-corner-short-configured, NCEM-enabled fill cells;
AACNT-AA-corner-short-configured, NCEM-enabled fill cells;
GATE-corner-short-configured, NCEM-enabled fill cells;
GATECNT-GATE-corner-short-configured, NCEM-enabled fill cells;
GATECNT-TS-corner-short-configured, NCEM-enabled fill cells;
GATECNT-corner-short-configured, NCEM-enabled fill cells;
GATECNT-AACNT-corner-short-configured, NCEM-enabled fill cells;
M1-corner-short-configured, NCEM-enabled fill cells;
V0-corner-short-configured, NCEM-enabled fill cells;
M1-V0-corner-short-configured, NCEM-enabled fill cells;
V1-M1-corner-short-configured, NCEM-enabled fill cells;
V1-corner-short-configured, NCEM-enabled fill cells;
M2-corner-short-configured, NCEM-enabled fill cells;
M2-V1-corner-short-configured, NCEM-enabled fill cells;
M3-corner-short-configured, NCEM-enabled fill cells;
V2-M2-corner-short-configured, NCEM-enabled fill cells;
V2-corner-short-configured, NCEM-enabled fill cells;
M3-V2-corner-short-configured, NCEM-enabled fill cells;
GATE-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;
GATE-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;
GATE-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;
GATECNT-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;
GATECNT-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;
V0-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;
V0-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;
V0-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;
V0-GATE-interlayer-overlap-short-configured, NCEM-enabled fill cells;
M1-GATECNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;
M1-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;
V1-V0-interlayer-overlap-short-configured, NCEM-enabled fill cells;
M2-M1-interlayer-overlap-short-configured, NCEM-enabled fill cells;
V2-V1-interlayer-overlap-short-configured, NCEM-enabled fill cells;
M3-M2-interlayer-overlap-short-configured, NCEM-enabled fill cells;
V0-GATECNT-via-chamfer-short-configured, NCEM-enabled fill cells;
V0-AACNT-via-chamfer-short-configured, NCEM-enabled fill cells;
V1-M1-via-chamfer-short-configured, NCEM-enabled fill cells;
V2-M2-via-chamfer-short-configured, NCEM-enabled fill cells;
V0-merged-via-short-configured, NCEM-enabled fill cells;
V1-merged-via-short-configured, NCEM-enabled fill cells;
and,
V2-merged-via-short-configured, NCEM-enabled fill cells;
a second DOE, comprising a plurality of similarly-configured, NCEM-enabled fill cells, wherein each NCEM-enabled fill cell comprises at least:
first and second elongated conductive supply rails, formed in a connector or interconnect stack layer, extending across the entire width of said cell, and configured for compatibility with corresponding supply rails contained in the logic cells of said standard cell region;
a NCEM pad, formed in a conductive layer, said NCEM pad being at least two times larger, in at least one dimension, than a minimum size permitted by design rules;
a rectangular test area defined by selected boundaries of at least first and second distinct, mask-patterned features, said test area being characterized by two dimensional parameters;
a first conductive pathway that electrically connects the first mask-patterned feature to said NCEM pad;
and,
a second conductive pathway that electrically connects the second mask-patterned feature to a permanently or virtually grounded structure;
wherein each of the similarly-configured, NCEM-enabled fill cells in the second DOE is configured to render a second selected manufacturing failure observable as an abnormally low pad-to-ground conductance or abnormally high pad-to-ground resistance, detected by VC inspection of the NCEM pad;
and,
wherein the similarly-configured, NCEM-enabled fill cells of the second DOE include a plurality of variants, where the variants differ in terms of their respective probability of presenting an abnormally low pad-to-ground conductance or abnormally high pad-to-ground resistance as a result of said second selected manufacturing failure;
and,
wherein the similarly-configured NCEM-enabled fill cells of the second DOE are selected from the list consisting of:
AA-snake-open-configured, NCEM-enabled fill cells;
TS-snake-open-configured, NCEM-enabled fill cells;
AACNT-snake-open-configured, NCEM-enabled fill cells;
GATE-snake-open-configured, NCEM-enabled fill cells;
GATECNT-snake-open-configured, NCEM-enabled fill cells;
V0-snake-open-configured, NCEM-enabled fill cells;
M1-snake-open-configured, NCEM-enabled fill cells;
V1-snake-open-configured, NCEM-enabled fill cells;
M2-snake-open-configured, NCEM-enabled fill cells;
V2-snake-open-configured, NCEM-enabled fill cells;
M3-snake-open-configured, NCEM-enabled fill cells;
AA-stitch-open-configured, NCEM-enabled fill cells;
TS-stitch-open-configured, NCEM-enabled fill cells;
AACNT-stitch-open-configured, NCEM-enabled fill cells;
GATECNT-stitch-open-configured, NCEM-enabled fill cells;
V0-stitch-open-configured, NCEM-enabled fill cells;
M1-stitch-open-configured, NCEM-enabled fill cells;
V1-stitch-open-configured, NCEM-enabled fill cells;
M2-stitch-open-configured, NCEM-enabled fill cells;
V2-stitch-open-configured, NCEM-enabled fill cells;
M3-stitch-open-configured, NCEM-enabled fill cells;
AACNT-TS-via-open-configured, NCEM-enabled fill cells;
AACNT-AA-via-open-configured, NCEM-enabled fill cells;
TS-AA-via-open-configured, NCEM-enabled fill cells;
GATECNT-GATE-via-open, NCEM-enabled fill cells;
V0-GATECNT-via-open-configured, NCEM-enabled fill cells;
V0-AA-via-open-configured, NCEM-enabled fill cells;
V0-TS-via-open-configured, NCEM-enabled fill cells;
V0-AACNT-via-open-configured, NCEM-enabled fill cells;
V0-GATE-via-open-configured, NCEM-enabled fill cells;
V0-via-open-configured, NCEM-enabled fill cells;
M1-V0-via-open-configured, NCEM-enabled fill cells;
V1-M1-via-open-configured, NCEM-enabled fill cells;
V1-M2-via-open-configured, NCEM-enabled fill cells;
M1-GATECNT-via-open-configured, NCEM-enabled fill cells;
M1-AANCT-via-open-configured, NCEM-enabled fill cells;
V2-M2-via-open-configured, NCEM-enabled fill cells;
V2-M3-via-open-configured, NCEM-enabled fill cells;
M1-metal-island-open-configured, NCEM-enabled fill cells;
M2-metal-island-open-configured, NCEM-enabled fill cells;
M3-metal-island-open-configured, NCEM-enabled fill cells;
V0-merged-via-open-configured, NCEM-enabled fill cells;
V0-AACNT-merged-via-open-configured, NCEM-enabled fill cells;
V0-GATECNT-merged-via-open-configured, NCEM-enabled fill cells;
V1-merged-via-open-configured, NCEM-enabled fill cells;
V2-merged-via-open-configured, NCEM-enabled fill cells;
V1-M1-merged-via-open-configured, NCEM-enabled fill cells;
and,
V2-M2-merged-via-open-configured, NCEM-enabled fill cells.

215 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/090,256Filed 4 Apr 2016 · us provisional application
Priority: 16 Dec 2015
Published: US 2017/0178981 A122 Jun 2017
Granted: 24 Oct 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification27 codes

H10P 74/238
Characterised by multiple measurements, corrections, marking or sorting processes: comprising acting in response to an ongoing measurement without…
G01R 31/2884
Testing of integrated circuits [IC]: using dedicated test connectors, test elements or test circuits on the IC under test
G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
H10D 62/115
Isolations within a component, i.e. internal isolations: dielectric isolations, e.g. air gaps