Integrated circuit device with improved layout

A method of making an integrated circuit device, the method comprising:

• forming a first instance of a device at a first location having a first cell layout;
• and
• forming a second instance of the device at a second location having a second cell layout;
• wherein the cell layouts include a device layer, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer,
• wherein the cell layouts conform with the equation M0_Enc≤(Max_M0_Length−Max_M1_Pitch_Length−VIA0_Width)/2, where:
• Max_M0_Length represents a maximum possible length of a line in the first metal interconnection layer in the cell layouts;
• Max_M1_Pitch_Length represents a maximum possible pitch between two lines in the second metal interconnection layer in the cell layouts;
• VIA0_Width represents a width of a via that connects a line in the first metal interconnection layer with a line in the second metal interconnection layer;
• and
• M0_Enc represents a distance from an outermost edge of the line in the first metal interconnection layer to an edge of a nearest possible via connecting the line in the first metal interconnection layer to the line in the second metal interconnection layer.

A method of making an integrated circuit device, the method comprising:

• forming a plurality of cells at respective cell locations in a substrate, each cell comprising:
• a device layer having device features spaced in accordance with a predetermined device pitch;
• a first interconnection layer disposed above the device layer and coupled to the device layer;
• and
• a second interconnection layer disposed above the first interconnection layer and coupled to the first interconnection layer through a first via layer,
• wherein the second interconnection layer has connection lines spaced in accordance with a predetermined line pitch, and
• wherein each cell conforms with the equation M0_Enc≤(Max_M0_Length-Max_M1_Pitch_Length−VIA0_Width)/2, where:
• Max_M0_Length represents a maximum possible length of a line in the first interconnection layer in the cell;
• Max_M1_Pitch_Length represents a maximum possible pitch between two lines in the second interconnection layer in the cell;
• VIA0_Width represents a width of a via that connects a line in the first interconnection layer with a line in the second interconnection layer;
• and
• M0_Enc represents a distance from an outermost edge of the line in the first interconnection layer to an edge of a nearest possible via connecting the line in the first interconnection layer to the line in the second interconnection layer.