Integrated circuit and method of forming the same

A non-transitory computer readable medium configured to store instructions, wherein the instructions are configured to be executed by a processor coupled to the non-transitory computer readable medium that cause the processor to perform a method comprising:

• generating a netlist of a first circuit, wherein the first circuit is configured as a non-functional circuit, and the first circuit includes a first pin, a second pin and a third pin that are electrically disconnected from each other, wherein generating the netlist of the first circuit comprises:
• grouping the first pin, the second pin and the third pin together into a first set of to be connected pins;
• generating a first cell layout of the first circuit, wherein the first cell layout includes a first conductive feature pattern corresponding to the first pin, a second conductive feature pattern corresponding to the second pin, and a third conductive feature pattern corresponding to the third pin;
• placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design, wherein placing the first cell layout by the APR tool comprises:
• connecting the first set of to be connected pins together, thereby changing the first circuit to a second circuit, the second circuit being configured as a functional version of the first circuit.

A method of forming an integrated circuit (IC), the method comprising:

• generating, by a processor, a netlist of a first circuit, wherein the first circuit is configured as a non-functional circuit, and the first circuit includes a first pin and a second pin that are electrically disconnected from each other, wherein generating the netlist of the first circuit comprises:
• labelling the first pin and the second pin as a first set of to be connected pins;
• and
• designating the first set of to be connected pins as a common group of pins that are to be connected together;
• generating, by the processor, a first cell layout of the first circuit, wherein the first cell layout includes a first conductive feature pattern corresponding to the first pin, and a second conductive feature pattern corresponding to the second pin, and being in a first layout level;
• placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design, wherein placing the first cell layout by the APR tool comprises:
• connecting the first set of to be connected pins in the common group of pins together, thereby changing the first circuit to a second circuit, the second circuit being configured as a functional version of the first circuit.