Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods

A complementary metal oxide semiconductor (MOS) (CMOS) standard cell circuit, comprising:

• a plurality of CMOS standard cells, each CMOS standard cell comprising:
• a first supply rail disposed in a direction in a first metal layer;
• a second supply rail disposed in the direction in the first metal layer;
• and
• a plurality of metal lines disposed in the direction in the first metal layer, wherein:
• each metal line of the plurality of metal lines corresponds to a track of a plurality of tracks;
• one or more metal lines of the plurality of metal lines have a cut edge corresponding to a first cell boundary of a corresponding CMOS standard cell;
• one or more metal lines of the plurality of metal lines have a cut edge corresponding to a second cell boundary of the corresponding CMOS standard cell, wherein the second cell boundary is on an opposite side of the corresponding CMOS standard cell compared to the first cell boundary;
• and
• one or more metal lines of the plurality of metal lines have an uncut edge corresponding to at least one of the first cell boundary and the second cell boundary;
• wherein:
• one or more CMOS standard cells of the plurality of CMOS standard cells are disposed such that the second cell boundary of the one or more CMOS standard cells is substantially adjacent to a first cell boundary of one or more other CMOS standard cells;
• and
• one or more metal lines of two or more CMOS standard cells form a single continuous metal line across corresponding tracks of the two or more CMOS standard cells.

A method for fabricating a CMOS standard cell circuit with dynamically cut metal lines in a first metal layer, comprising:

• determining placement of a plurality of metal lines and interconnects disposed above a first metal layer in one or more CMOS standard cells;
• determining if a first metal layer layout optimizer is available;
• responsive to determining that the first metal layer layout optimizer is available, determining a layout of a plurality of instances of the one or more CMOS standard cells, wherein placement of the plurality of metal lines disposed in the first metal layer in the layout of each instance of the one or more CMOS standard cells is based on an optimized placement of the plurality of metal lines disposed in the first metal layer using orientation and adjacency variables of the one or more CMOS standard cells and a plurality of cell variation templates that define physical attributes of each layout;
• responsive to determining that the first metal layer layout optimizer is not available, providing the layout of the plurality of instances of the one or more CMOS standard cells, wherein placement of the plurality of metal lines disposed in the first metal layer in the layout of each instance of the one or more CMOS standard cells corresponds to the placement of the plurality of metal lines disposed in the first metal layer in the plurality of cell variation templates;
• for each layout of each instance of the plurality of instances of the one or more CMOS standard cells, determining a plurality of corresponding design costs;
• building one or more first metal layer cost-based trees based on one or more corresponding variation seeds, each first metal layer cost-based tree comprising the plurality of design costs corresponding to a combination of the layouts of the one or more CMOS standard cells associated with the corresponding variation seed;
• determining the first metal layer cost-based tree that includes the plurality of design costs corresponding to a figure of merit;
• and
• disposing and cutting the plurality of metal lines in the first metal layer according to the layout of each of the one or more CMOS standard cells of the determined first metal layer cost-based tree.