H10D 84/975
Wiring regions or routing
Official title: {Wiring regions or routing}
H10D84/975 (Wiring regions or routing) appears on 507 US grants and 562 published applications in this corpus.
Search patents in H10D- Granted patents
- 507
- Published applications
- 562
- Assignees
- 57
- Inventors
- 649
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2006 | 0 | 1 |
| 2007 | 0 | 1 |
| 2008 | 2 | 0 |
| 2009 | 0 | 2 |
| 2010 | 1 | 88 |
| 2011 | 18 | 0 |
| 2012 | 45 | 2 |
| 2013 | 15 | 23 |
| 2014 | 26 | 7 |
| 2015 | 11 | 10 |
| 2016 | 13 | 14 |
| 2017 | 40 | 30 |
| 2018 | 47 | 42 |
| 2019 | 58 | 50 |
| 2020 | 42 | 36 |
| 2021 | 43 | 47 |
| 2022 | 26 | 38 |
| 2023 | 31 | 45 |
| 2024 | 29 | 50 |
| 2025 | 37 | 41 |
| 2026 | 23 | 35 |
By publication year. 2026 runs to 8 Oct.
Recent patents
- Hybrid cell height design with a backside power distribution network29 Sep 2026US 12,751,083 B2International Business Machines Corporation
- Backside programmable gate array1 Sep 2026US 12,727,242 B2International Business Machines Corporation
- VTFET circuit with optimized MOL25 Aug 2026US 12,720,860 B2International Business Machines Corporation
- Integrated circuit and method of manufacturing the same18 Aug 2026US 12,713,684 B2Samsung Electronics Co., Ltd.
- Integrated circuit structure with front side signal lines and backside power delivery4 Aug 2026US 12,701,782 B2Intel Corporation
- Device Disaggregation For Improved Performance27 Aug 2026US 2026/0255673 A1Adeia Semiconductor Inc.
- Patterning Method Applicable in Semiconductor Processing20 Aug 2026US 2026/0247939 A1Imec Vzw
- Semiconductor device and method of fabricating the same13 Aug 2026US 2026/0239735 A1Samsung Electronics Co., Ltd.
- Integrated circuit device with varied conductor arrangement, and method of generating a layout using the same30 Jul 2026US 2026/0223460 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Standard cell including interconnection structure23 Jul 2026US 2026/0214984 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- Dynamic array architecture227US 7,446,352 B2Tela Innovations, Inc. · 2008
- Integrated circuit having gate electrode level region including at least four linear-shaped conductive structures with some outer-contacted linear-shaped conductive structures having larger outer extending portion than inner extending portion159US 8,134,184 B2Tela Innovations, Inc. · 2012
- Dynamic array architecture142US 7,842,975 B2Tela Innovations, Inc. · 2010
- Semiconductor device having at least three linear-shaped electrode level conductive features of equal length positioned side-by-side at equal pitch141US 8,058,671 B2Tela Innovations, Inc. · 2011
- Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segment140US 7,910,958 B2Tela Innovations, Inc. · 2011