H10D 84/968
Macro-architecture
Official title: {Macro-architecture}
H10D84/968 (Macro-architecture) appears on 811 US grants and 1,099 published applications in this corpus.
Search patents in H10D- Granted patents
- 811
- Published applications
- 1,099
- Assignees
- 89
- Inventors
- 1,051
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2006 | 0 | 2 |
| 2007 | 0 | 1 |
| 2008 | 2 | 0 |
| 2009 | 1 | 5 |
| 2010 | 1 | 89 |
| 2011 | 22 | 5 |
| 2012 | 47 | 11 |
| 2013 | 22 | 30 |
| 2014 | 34 | 15 |
| 2015 | 21 | 22 |
| 2016 | 21 | 26 |
| 2017 | 56 | 51 |
| 2018 | 61 | 61 |
| 2019 | 79 | 75 |
| 2020 | 67 | 71 |
| 2021 | 67 | 84 |
| 2022 | 47 | 83 |
| 2023 | 68 | 107 |
| 2024 | 75 | 110 |
| 2025 | 82 | 100 |
| 2026 | 38 | 151 |
By publication year. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Hybrid cell height design with a backside power distribution network29 Sep 2026US 12,751,083 B2International Business Machines Corporation
- Method and IC design with non-linear power rails29 Sep 2026US 12,751,260 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Backside programmable gate array1 Sep 2026US 12,727,242 B2International Business Machines Corporation
- VTFET circuit with optimized MOL25 Aug 2026US 12,720,860 B2International Business Machines Corporation
- Compatible hybrid-cell structure, device having the same, and method25 Aug 2026US 12,720,861 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Integrated circuit device1 Oct 2026US 2026/0304952 A1Samsung Electronics Co., Ltd.
- Semiconductor structure1 Oct 2026US 2026/0304954 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Device Disaggregation For Improved Performance27 Aug 2026US 2026/0255673 A1Adeia Semiconductor Inc.
- Patterning Method Applicable in Semiconductor Processing20 Aug 2026US 2026/0247939 A1Imec Vzw
- Semiconductor device and method of fabricating the same13 Aug 2026US 2026/0239735 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- Dynamic array architecture227US 7,446,352 B2Tela Innovations, Inc. · 2008
- Integrated circuit having gate electrode level region including at least four linear-shaped conductive structures with some outer-contacted linear-shaped conductive structures having larger outer extending portion than inner extending portion159US 8,134,184 B2Tela Innovations, Inc. · 2012
- Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same152US 7,888,705 B2Tela Innovations, Inc. · 2011
- Semiconductor device with dynamic array section148US 7,917,879 B2Tela Innovations, Inc. · 2011
- Dynamic array architecture142US 7,842,975 B2Tela Innovations, Inc. · 2010