Hybrid cell height design with a backside power distribution network

A multi-layer integrated circuit (IC) having a three-dimensional structure formed along an x-axis, a y-axis, and a z-axis, the multi-layer IC comprising:

• a first region at a first side of a wafer;
• a second region at a second side of the wafer that is opposite the first side of the wafer;
• a third region of the wafer between the first region and the second region;
• a set of signal lines in the first region;
• power rails in the second region, the power rails comprising a first set of power rails and a second set of power rails;
• a first cell positioned in the third region;
• a second cell adjacent to the first cell and positioned in the third region;
• and
• a backside power distribution network (BSPDN) electrically coupled to the power rails;
• wherein the first cell comprises:
• first cell logic gates configured to perform a first cell logic function;
• and
• first cell tracks comprising a first portion of the set of signal lines and a first portion of the power rails;
• wherein the second cell comprises:
• second cell logic gates configured to perform a second cell logic function;
• and
• second cell tracks comprising a second portion of the set of signal lines and a second portion of the power rails;
• wherein the set of signal lines comprises a signal-line pitch between each signal line in the set of signal lines;
• wherein a first power-rail pitch between each power rail in the first set of power rails is different than a second power-rail pitch between each power rail in the second set of power rails;
• and
• wherein the first power-rail pitch and the second power-rail pitch substantially vary from one another, and the signal-line pitch does not substantially vary.

A multi-layer integrated circuit (IC) structure comprising:

• a back-end-of-line (BEOL) region at a first side of a wafer;
• a backside region at a second side of the wafer that is opposite the first side of the wafer;
• a front-end-of-line (FEOL) region of the wafer between the BEOL region and the backside region;
• a set of signal lines in the BEOL region;
• power rails in the backside region, the power rails comprising a first set of power rails and a second set of power rails;
• a first cell positioned in the FEOL region and having a first cell height;
• a second cell adjacent to the first cell, positioned in the FEOL region, and having a second cell height that is greater than the first cell height;
• and
• a backside power distribution network (BSPDN) electrically coupled to the set of power rails;
• wherein the first cell comprises:
• first cell logic gates configured to perform a first cell logic function;
• and
• first cell tracks comprising a first portion of the set of signal lines and a first portion of the power rails;
• wherein the second cell comprises:
• second cell logic gates configured to perform a second cell logic function;
• and
• second cell tracks comprising a second portion of the set of signal lines and a second portion of the power rails;
• wherein the set of signal lines comprises a signal-line pitch between each signal line in the set of signal lines;
• wherein a first power-rail pitch between each power rail in the first set of power rails is different than a second power-rail pitch between each power rail in the second set of power rails;
• and
• wherein the first power-rail pitch and the second power-rail pitch substantially vary from one another, and the signal-line pitch does not substantially vary.