Patterning Method Applicable in Semiconductor Processing

A patterning method applicable in a semiconductor production process, comprising the steps of:

• producing a stack of at least two layers on a support substrate,
• by lithography and anisotropic etching, producing an opening through the stack of at least two layers,
• thereafter applying at least a first directional etching process step, using an etch beam configured to remove the material of one or more upper layers of the stack selectively with respect to the layer or layers directly underneath the one or more upper layers, to thereby enlarge the opening in the one or more upper layers while essentially maintaining the in-plane dimensions of the opening in the layer or layers directly underneath the one or more upper layers.