Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
AssigneeTela Innovations, Inc.
InventorsScott T. Becker, Michael C. Smayling
Life of this patent
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Abstract
A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the boundary of the dynamic array section. The method further includes controlling chip layout features within the manufacturing assurance halo to ensure that manufacturing of conductive features inside the boundary of the dynamic array section is not adversely affected by chip layout features within the manufacturing assurance halo.
Claims22
A method for defining a dynamic array section to be manufactured on a semiconductor chip, comprising:
- defining a peripheral boundary of the dynamic array section;
- defining a manufacturing assurance halo outside the boundary of the dynamic array section;
- and
- controlling chip layout features within the manufacturing assurance halo to ensure that manufacturing of conductive features inside the boundary of the dynamic array section is not adversely affected by chip layout features within the manufacturing assurance halo.
A method for designing a semiconductor chip having one or more functionally interfaced dynamic array sections, comprising:
- selecting a dynamic array section to be defined on a portion of the chip, the selected dynamic array section having an associated manufacturing assurance halo defined outside a boundary of the selected dynamic array section;
- and
- placing the selected dynamic array section within a layout of the portion of the chip such that layout features not associated with the selected dynamic array section and within the manufacturing assurance halo are compatible with the manufacturing assurance halo so as to avoid adversely impacting manufacturability of the selected dynamic array section.
A semiconductor chip, comprising:
- a dynamic array section having a peripheral boundary, the dynamic array section defined by a plurality of levels of the chip within the peripheral boundary, the dynamic array section including a number of linear conductive features defined within each of the plurality of levels of the chip, wherein each linear conductive feature is defined along a line of a virtual grate associated with the level of the chip within which the linear conductive feature is defined;
- and
- a manufacturing assurance halo defined around the dynamic array section, wherein a number of the linear conductive features defined within the dynamic array section are defined to extend outside the peripheral boundary of the dynamic array section through the manufacturing assurance halo.
Dependencies are inferred from the claim text.