Integrated circuit and method of manufacturing the same

An integrated circuit comprising a plurality of metal layers, which are stacked, the integrated circuit comprising:

• a first logic cell and a second logic cell, at least one of which comprising a plurality of patterns respectively formed on the plurality of metal layers, wherein a first metal layer among the plurality of metal layers comprises patterns extending in a first direction and a plurality of first tracks spaced apart in a second direction;
• and
• a dummy pattern formed on a first track among the plurality of first tracks over the first logic cell, the second logic cell and a cell boundary between the first logic cell and the second logic cell in the first metal layer, wherein the dummy pattern is separated from other patterns on the first metal layer,
• wherein the dummy pattern comprises a conductive material.

An integrated circuit comprising a plurality of metal layers, which are stacked, the integrated circuit comprising:

• a first standard cell and a second standard cell, at least one of which comprises a plurality of patterns respectively formed on the plurality of metal layers, wherein a metal layer among the plurality of metal layers comprises patterns extending in a first direction and a plurality of first tracks spaced apart in a second direction;
• and
• an extension pattern formed on a first track among the plurality of first tracks over the first standard cell and the second standard cell in the metal layer, wherein the extension pattern is formed between two patterns on the first track and extends from a pattern among the two patterns,
• wherein the extension pattern extends from one of the two patterns,
• wherein the two patterns are adjacent each other and spaced apart by at least one designated value, and
• wherein the two patterns and the extension pattern comprise a conductive material.