Integrated circuit device with varied conductor arrangement, and method of generating a layout using the same

An integrated circuit device comprising:

• a first insulating structure and a second insulating structure spaced apart from the first insulating structure in a first direction, each of the first and second insulating structures extending in a second direction perpendicular to the first direction;
• a first conductive segment on a first peripheral track of a first conductive layer, the first peripheral track extending in the first direction;
• a second conductive segment on a second track of the first conductive layer, the second track being between the first insulating structure and the second insulating structure, and extending parallel to the first peripheral track;
• a first gap extending in the second direction in the first conductive layer at an end of the first conductive segment, the first gap being between the first insulating structure and the second insulating structure along the first direction;
• a second gap extending in the second direction in the first conductive layer at an end of the second conductive segment, the second gap partially overlapping the second insulating structure;
• and
• a first gate structure between the first insulating structure and the second insulating structure, and overlapped by the first gap,
• wherein:
• the first conductive segment is recessed in the first direction away from the second insulating structure.

A method of manufacturing an integrated circuit device, the method comprising:

• arranging one or more rectangular standard cells in one or more rows to form a first layout;
• replacing one or more of the rectangular standard cells of the first layout with a non-rectangular standard cell to form a second layout, wherein the non-rectangular standard cell includes:
• a first insulating pattern and a second insulating pattern spaced apart from the first insulating pattern in a first direction, each of the first and second insulating patterns extending in a second direction perpendicular to the first direction;
• a first conductor pattern on a first peripheral track of a first conductive layer, the first peripheral track extending in the first direction;
• a second conductor pattern on a second track of the first conductive layer, the second track being between the first insulating pattern and the second insulating pattern, and extending parallel to the first peripheral track;
• a first cut pattern extending in the second direction in the first conductive layer at a first end of the first conductor pattern;
• a second cut pattern extending in the second direction in the first conductive layer at a first end of the second conductor pattern, the second cut pattern partially overlapping the first insulating pattern;
• and
• a first gate pattern between the first insulating pattern and the second insulating pattern, and extending in the second direction adjacent to the second cut pattern,
• wherein:
• the second cut pattern is between the first cut pattern and the first gate pattern along the first direction,
• the first insulating pattern is between the first cut pattern and the first gate pattern along the first direction, and
• the first conductor pattern extends in the first direction away from the first gate pattern to protrude beyond the second cut pattern;
• forming a first insulating structure and a second insulating structure on a substrate, the first and second insulating structures corresponding to the first and second insulating patterns;
• forming a first gate structure on the substrate, the first gate structure corresponding to the first gate pattern;
• forming a first conductor in the first conductive layer on the first peripheral track;
• forming a second conductor in the first conductive layer on the second track;
• etching the first conductor to form a first gap in the first conductor corresponding to the first cut pattern;
• and
• etching the second conductor to form a second gap in the first conductor corresponding to the second cut pattern.