H10D 64/668
The layer being a silicide
Official title: {the layer being a silicide, e.g. TiSi2}
H10D64/668 (The layer being a silicide) appears on 664 US grants and 747 published applications in this corpus.
Search patents in H10D- Granted patents
- 664
- Published applications
- 747
- Assignees
- 166
- Inventors
- 1,230
- Latest grant
- 30 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1981 | 1 | 0 |
| 1982 | 2 | 0 |
| 1983 | 3 | 0 |
| 1984 | 2 | 0 |
| 1985 | 2 | 0 |
| 1986 | 3 | 0 |
| 1987 | 1 | 0 |
| 1988 | 3 | 0 |
| 1989 | 3 | 0 |
| 1990 | 2 | 0 |
| 1991 | 1 | 0 |
| 1992 | 2 | 0 |
| 1993 | 1 | 0 |
| 1994 | 0 | 0 |
| 1995 | 1 | 0 |
| 1996 | 3 | 0 |
| 1997 | 4 | 0 |
| 1998 | 6 | 0 |
| 1999 | 8 | 0 |
| 2000 | 7 | 0 |
| 2001 | 7 | 1 |
| 2002 | 9 | 4 |
| 2003 | 12 | 11 |
| 2004 | 5 | 14 |
| 2005 | 6 | 23 |
| 2006 | 26 | 40 |
| 2007 | 15 | 40 |
| 2008 | 19 | 64 |
| 2009 | 30 | 54 |
| 2010 | 50 | 39 |
| 2011 | 31 | 20 |
| 2012 | 20 | 21 |
| 2013 | 25 | 29 |
| 2014 | 32 | 35 |
| 2015 | 40 | 54 |
| 2016 | 46 | 43 |
| 2017 | 39 | 44 |
| 2018 | 47 | 35 |
| 2019 | 39 | 35 |
| 2020 | 24 | 16 |
| 2021 | 20 | 28 |
| 2022 | 19 | 13 |
| 2023 | 11 | 14 |
| 2024 | 19 | 16 |
| 2025 | 13 | 31 |
| 2026 | 5 | 23 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process30 Jun 2026US 12,672,319 B2Sony Group Corporation
- Connector via structures for nanostructures and methods of forming the same9 Jun 2026US 12,652,821 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device comprising alignment key19 May 2026US 12,635,218 B2Samsung Electronics Co., Ltd.
- CMOS architecture with thermally stable silicide gate workfunction metal10 Mar 2026US 12,575,184 B2Intel Corporation
- Methods for reliably forming microelectronic devices with conductive contacts to silicide regions10 Feb 2026US 12,550,692 B2
- Structure including an interfacial layer and method of forming same8 Oct 2026US 2026/0314003 A1ASM IP Holding B. V.
- Semiconductor device and fabrication method thereof24 Sep 2026US 2026/0293235 A1United Microelectronics Corp.
- Method of manufacturing semiconductor device including buried connector17 Sep 2026US 2026/0282491 A1Samsung Electronics Co., Ltd.
- Method for forming a source/drain contact for a transistor6 Aug 2026US 2026/0231504 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method for preventing voids in contact plugs using selective passivation layers in semiconductor fabrication2 Jul 2026US 2026/0190432 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Method for the manufacture of an insulated gate field effect semiconductor device359US 6,784,033 B1Semiconductor Energy Laboratory Co.Ltd. · 2004
- Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions258US 5,960,270 AMotorola, Inc. · 1999
- MOS transistor having a composite gate electrode and method of fabrication126US 5,625,217 AIntel Corporation · 1997
- Method and apparatus for creating a voltage threshold in a FET120US 6,472,278 B1Motorola, Inc. · 2002
- Method of frabricating a MOS transistor having a composite gate electrode116US 5,783,478 AIntel Corporation · 1998