Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions

A method of forming a semiconductor structure, wherein the method comprises the steps of:

• providing a semiconductor substrate;
• forming a dopant-containing region over the semiconductor substrate, the dopant-containing region containing dopant atoms;
• forming a dielectric layer over the dopant-containing region;
• forming an opening through the dielectric layer and the dopant-containing region to expose a portion of the semiconductor substrate;
• forming at least one doped region in the semiconductor substrate by thermally driving the dopant atoms from the dopant-containing region into the semiconductor substrate, the at least one doped region being self-aligned to at least one edge of the opening;
• and
• filling the opening with a metal to form a metal gate region.

A method of forming a semiconductor structure, wherein the method comprises the steps of:

• providing a semiconductor substrate;
• forming a temporary feature having a first side and a second side over the semiconductor substrate;
• forming a first doped region in the semiconductor substrate directly adjacent to the first side of the temporary feature and a second doped region in the semiconductor substrate directly adjacent to the second side of the temporary feature;
• forming a dielectric layer over the semiconductor substrate;
• planarizing a top surface of the dielectric layer to expose a top portion of the temporary feature while leaving bottom-most regions of the dielectric layer on the surface of the semiconductor structure;
• removing the temporary feature to form an opening in the dielectric layer;
• and
• filling the opening with a metal to create a metal gate electrode.

A method of forming a semiconductor structure, wherein the method comprises the method of:

• providing a semiconductor substrate;
• forming a self-alignment feature over a portion the semiconductor substrate;
• implanting a first region of the semiconductor substrate with a dopant;
• and
• forming a metal gate, whereby no polysilicon region is directly adjacent a gate dielectric region, following the step of implanting, wherein the metal gate is formed substantially over the portion of the semiconductor substrate.

A method for forming a semiconductor structure, the method comprising the steps of:

• forming a first dielectric layer;
• forming an etch stop layer over the first dielectric layer;
• forming a second dielectric layer over the first dielectric layer;
• etching a dual inlaid structure into the first and second dielectric layers wherein the first dielectric layer contains an opening defining a first portion of the dual inlaid structure and the second dielectric layer contains an opening defining a second portion of the dual inlaid structure wherein the opening in the second dielectric layer has a width dimension greater than a width dimension of the opening in the first dielectric layer;
• and
• forming a metallic electrical device electrode within the first portion of the dual inlaid structure and a metallic interconnect coupled to the metallic electrical device electrode within the second portion of the dual inlaid structure.

A method for forming a semiconductor structure, the method comprising the steps of:

• providing a semiconductor substrate containing dielectric isolation regions;
• forming a feature region over the semiconductor substrate;
• forming doped regions within the semiconductor substrate using the feature region as a self alignment feature, the doped regions forming both a source region and a drain region for the semiconductor structure in a self-aligned manner to the feature region;
• forming a gate dielectric layer within the feature region;
• at least partially filling the feature region with a first metallic layer which overlies the gate dielectric layer;
• polishing the first metallic layer to form a first metallic plug region within the feature region;
• forming interconnect openings on top of the dielectric isolation regions within the semiconductor substrate;
• forming a second metallic layer within the interconnect openings and any remaining portion of the feature region;
• and
• polishing the second metallic layer to form a second metallic plug regions in the interconnect openings and any remaining portion of the feature region.