Semiconductor device comprising alignment key

A semiconductor device comprising:

• a substrate comprising an active pattern;
• a channel pattern on the active pattern, the channel pattern comprising a plurality of semiconductor patterns that are spaced apart from each other and are vertically stacked;
• a source/drain pattern connected to the plurality of semiconductor patterns;
• a through pattern penetrating the source/drain pattern;
• a metal-semiconductor compound layer between the source/drain pattern and the through pattern;
• an active contact on the through pattern;
• and
• a buried connector in the substrate and connected to the through pattern,
• wherein the active contact is aligned with the through pattern and is connected to an upper surface of the through pattern, and
• wherein the buried connector is aligned with the through pattern and is connected to a bottom surface of the through pattern.

A semiconductor device comprising:

• a substrate comprising an active region;
• a device isolation layer defining an active pattern on the active region;
• a source/drain pattern on the active pattern;
• a channel pattern on the active pattern, the channel pattern comprising a plurality of semiconductor patterns that are spaced apart from each other and are vertically stacked;
• a gate electrode on the plurality of semiconductor patterns, the gate electrode comprising:
• inner electrodes between adjacent semiconductor patterns of the plurality of semiconductor patterns, and
• an outer electrode on an uppermost semiconductor pattern of the plurality of semiconductor patterns;
• a gate insulating layer between the adjacent semiconductor patterns and the gate electrode;
• a gate spacer on a sidewall of the gate electrode;
• a gate capping pattern on an upper surface of the gate electrode;
• a gate cutting pattern penetrating the gate electrode;
• a through pattern penetrating the source/drain pattern and connected to the source/drain pattern;
• a metal-semiconductor compound layer between the source/drain pattern and the through pattern;
• an interlayer insulating layer at least partially covering the source/drain pattern, the gate capping pattern, and the through pattern;
• an active contact penetrating the interlayer insulating layer such that the active contact is connected to the through pattern;
• a gate contact penetrating the interlayer insulating layer and the gate capping pattern such that the gate contact is connected to the gate electrode;
• a first metal layer on the interlayer insulating layer, the first metal layer comprising:
• a power wiring;
• and
• first wirings connected to the active contact and the gate contact, respectively;
• a second metal layer on the first metal layer, the second metal layer comprising second wirings connected to the first metal layer;
• a buried connector extending from the through pattern toward a bottom surface of the substrate;
• buried spacers on sides of the buried connector;
• a backside interconnection layer on the bottom surface of the substrate, the backside interconnection layer being connected to the buried connector;
• and
• a power transmission network layer on a bottom surface of the backside interconnection layer,
• wherein the active contact, the through pattern, and the buried connector are aligned with each other in a direction perpendicular to a surface of the substrate.