Connector via structures for nanostructures and methods of forming the same

A device structure comprising:

• a field effect transistor located on a front surface of a backside insulating matrix layer and comprising a first active region and a second active region which comprises a source region and a drain region;
• a first dummy gate structure and a second dummy gate structure located on a sidewall of the first active region;
• a first backside metal interconnect structure and a second backside metal interconnect structure that are located on a bottom surface of the backside insulating matrix layer;
• a first electrically conductive path connecting the first active region and the first backside metal interconnect structure;
• and
• a second electrically conductive path connecting the second active region and the second backside metal interconnect structure.

A device structure comprising:

• a semiconductor nanostructure located on a front surface of a backside insulating matrix layer and comprising:
• at least one semiconductor channel plate;
• a gate structure comprising a gate dielectric layer, a gate electrode, a dielectric gate spacer, and dielectric channel spacers;
• and
• a first active region and a second active region located at end portions of the at least one semiconductor channel plate and comprising a source region and a drain region;
• a backside metal interconnect structure located on a bottom surface of the backside insulating matrix layer;
• and
• an electrically conductive path connecting the first active region and the backside metal interconnect structure and comprising a connector via structure in contact with a dummy gate structure.