H10B 12/34
The transistor being at least partially in a trench in the substrate
Official title: {the transistor being at least partially in a trench in the substrate}
H10B12/34 (The transistor being at least partially in a trench in the substrate) appears on 1,755 US grants and 2,275 published applications in this corpus.
Search patents in H10B- Granted patents
- 1,755
- Published applications
- 2,275
- Assignees
- 143
- Inventors
- 2,444
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 4 | 0 |
| 1979 | 1 | 0 |
| 1980 | 4 | 0 |
| 1981 | 2 | 0 |
| 1982 | 3 | 0 |
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 2 | 0 |
| 1991 | 1 | 0 |
| 1992 | 1 | 0 |
| 1993 | 4 | 0 |
| 1994 | 5 | 0 |
| 1995 | 8 | 0 |
| 1996 | 10 | 0 |
| 1997 | 4 | 0 |
| 1998 | 11 | 0 |
| 1999 | 13 | 0 |
| 2000 | 18 | 0 |
| 2001 | 13 | 4 |
| 2002 | 16 | 11 |
| 2003 | 14 | 16 |
| 2004 | 13 | 17 |
| 2005 | 15 | 18 |
| 2006 | 12 | 35 |
| 2007 | 19 | 36 |
| 2008 | 27 | 36 |
| 2009 | 30 | 36 |
| 2010 | 29 | 32 |
| 2011 | 28 | 32 |
| 2012 | 32 | 53 |
| 2013 | 43 | 47 |
| 2014 | 41 | 44 |
| 2015 | 54 | 90 |
| 2016 | 73 | 66 |
| 2017 | 52 | 51 |
| 2018 | 71 | 90 |
| 2019 | 89 | 115 |
| 2020 | 105 | 124 |
| 2021 | 115 | 162 |
| 2022 | 123 | 215 |
| 2023 | 149 | 326 |
| 2024 | 158 | 247 |
| 2025 | 210 | 181 |
| 2026 | 129 | 191 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Memory cell with reduced parasitic capacitance and conductive via extending into source/drain region6 Oct 2026US 12,757,383 B2Nanya Technology Corporation
- Memory cell with reduced parasitic capacitance and spacer between u-shaped liner and air gap6 Oct 2026US 12,757,384 B2Nanya Technology Corporation
- Semiconductor device and manufacturing method thereof6 Oct 2026US 12,757,387 B2Nanya Technology Corporation
- Semiconductor device comprising trench gate along with separation layers29 Sep 2026US 12,751,002 B2Samsung Electronics Co., Ltd.
- Semiconductor device and method for forming the same22 Sep 2026US 12,745,385 B2SK hynix Inc.
- Semiconductor device with low-k spacer8 Oct 2026US 2026/0313877 A1SK hynix Inc.
- Memory device and method for forming the same1 Oct 2026US 2026/0304742 A1Nanya Technology Corporation
- Semiconductor device1 Oct 2026US 2026/0304800 A1SK hynix Inc.
- Capacitor comprising anti-ferroelectric layers and high-k dielectric layers1 Oct 2026US 2026/0304801 A1SK hynix Inc.
- Apparatus including cell contact and redistribution layer structure1 Oct 2026US 2026/0305313 A1Micron Technology, Inc.
Most cited
By later US patents
- Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region290US 6,686,624 B2Monolithic System Technology, Inc. · 2004
- 4 F2 folded bit line DRAM cell structure having buried bit and word lines285US 6,689,660 B1Micron Technology, Inc. · 2004
- Integrated circuit with buried digit line264US 8,102,008 B2Micron Technology, Inc. · 2012
- Method and structure for a 1T-RAM bit cell and macro263US 7,425,740 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2008
- High-density DRAM structure on soi259US 5,528,062 AInternational Business Machines Corporation · 1996