Memory cell with reduced parasitic capacitance and conductive via extending into source/drain region

A memory cell, comprising:

• a substrate;
• a word line, arranged within the substrate;
• a first source/drain region;
• a second source/drain region, wherein the first source/drain region and the second source/drain region are disposed in the substrate and on opposite sides of the word line;
• a first conductive via, disposed on the first source/drain region;
• a second conductive via, disposed on the second source/drain region, comprising:
• a lower portion, extending into the second source/drain region;
• and
• an upper portion, disposed over the lower portion;
• a first conductive line, disposed over the first conductive via;
• a second conductive line, disposed over the second conductive via;
• and
• an isolation region, disposed within the substrate, wherein the lower portion is free of being contact with the isolation region;
• wherein the word line comprises:
• a first gate electrode arranged within the substrate;
• a second gate electrode arranged within the substrate and over the first gate electrode;
• and
• a gate dielectric layer separating the substrate from the first gate electrode and the second gate electrode from the substrate, wherein the gate dielectric layer comprises:
• a first dielectric layer arranged within the substrate and laterally surrounding the first gate electrode;
• a second dielectric layer over the first dielectric layer and laterally surrounding the second gate electrode;
• and
• a low-k layer arranged over the first dielectric layer and laterally surrounded by the second dielectric layer, wherein the low-k layer has a dielectric constant less than that of the first dielectric layer or the second dielectric layer;
• wherein the gate dielectric layer further comprises a third dielectric layer disposed over the low-k layer and the second dielectric layer.