Memory cell with reduced parasitic capacitance and spacer between u-shaped liner and air gap
AssigneeNanya Technology Corporation
InventorPing Hsu
Life of this patent
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Abstract
A memory cell includes a substrate, a word line, a first source/drain region, a second source/drain region, a first conductive via, and a second conductive via. The word line is arranged within the substrate. The first source/drain region and the second source/drain region are disposed in the substrate and on opposite sides of the word line. The first conductive via is disposed on the first source/drain region. The second conductive via is disposed on the second source/drain region. The second conductive includes a lower portion and an upper portion. The lower portion is extending into the second source/drain region. The upper portion is disposed over the lower portion.
Claims10
A memory cell, comprising:
- a substrate;
- a word line, arranged within the substrate;
- a first source/drain region;
- a second source/drain region, wherein the first source/drain region and the second source/drain region are disposed in the substrate and on opposite sides of the word line;
- a dielectric layer, disposed over the word line, the first source/drain region, and the second source/drain region;
- a first conductive via, disposed in the dielectric layer and on the first source/drain region;
- and
- a second conductive via, disposed in the dielectric layer and on the second source/drain region,
- wherein the first conductive via comprises:
- a liner, having a U-shaped profile and in contact with the first source/drain region;
- a bit line contact, disposed over the liner and surrounded by the liner;
- a first air gap;
- and
- a spacer, sandwiched between the liner and the first air gap.
Dependencies are inferred from the claim text.