Semiconductor device comprising trench gate along with separation layers

A semiconductor device, comprising:

• a substrate including an active region between device separation layers;
• a word line intersecting and overlapping the active region;
• a word line capping layer covering a top surface of the word line;
• a plurality of bit lines interacting and overlapping the active region and extending in a different direction from an extension direction of the word line;
• a plurality of buried contacts each connected to the active region;
• a plurality of direct contacts each connecting the active region to a corresponding one of the plurality of bit lines;
• a fence pattern on top of the word line capping layer;
• and
• a landing pad connected to a corresponding one of the plurality of buried contacts,
• wherein the fence pattern is within a fence pattern trench, the fence pattern trench being at a corresponding space between the plurality of bit lines and between the plurality of buried contacts,
• a top surface of the word line capping layer is recessed along a bottom surface of the fence pattern trench,
• the fence pattern includes a first fence pattern, a second fence pattern, and a third fence pattern stacked sequentially within the fence pattern trench,
• the first fence pattern and the third fence pattern include a first material,
• the second fence pattern includes a second material having different permittivity from the first material, and
• at least one of a first length of the first fence pattern, a second length of the second fence pattern, and a third length of the third fence pattern is different.

A semiconductor device, comprising:

• a substrate including an active region between device separation layers;
• a word line intersecting and overlapping the active region;
• a word line capping layer covering a top surface of the word line;
• a plurality of bit lines interacting and overlapping the active region and extending in a different direction from an extension direction of the word line;
• a plurality of buried contacts each connected to the active region;
• a plurality of direct contacts each connecting the active region to a corresponding one of the plurality of bit lines;
• a fence pattern on top of the word line capping layer;
• and
• a landing pad connected to a corresponding one of the plurality of buried contacts,
• wherein the fence pattern is within a fence pattern trench, the fence pattern trench being at a corresponding space between the plurality of bit lines and between the plurality of buried contacts,
• a top surface of the word line capping layer is recessed along a bottom surface of the fence pattern trench,
• each of the plurality of bit lines includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially,
• the fence pattern includes a first fence pattern, a second fence pattern, and a third fence pattern,
• at least one of the first fence pattern, the second fence pattern, and the third fence pattern includes a different material, and
• at least one of a first width of the first fence pattern, a second width of the second fence pattern, and a third width of the third fence pattern is different.