Method and structure for a 1T-RAM bit cell and macro

An integrated circuit including a logic region and an embedded memory region, comprising:

• a semiconductor substrate having shallow trench isolation regions formed within it containing an trench insulator;
• at least one planar MOS transistor formed over said semiconductor substrate in a logic region, the logic region isolated from the embedded memory region by at least one shallow trench isolation region;
• at least one finFET transistor formed on a silicon fin in the embedded memory region, the silicon fin being formed between two adjacent shallow trench isolation regions;
• and
• at least one metal-insulator-metal (MIM) capacitor formed in the memory region above the substrate, the at least one MIM capacitor comprising a first conductive layer, a dielectric layer disposed over the first conductive layer, and a second conductive layer formed over the dielectric layer, and wherein the first conductive layer is coupled to the finFET transistor.

An integrated circuit formed of a plurality of macro cells coupled together to perform a function, at least one of the macro cells comprising:

• a semiconductor substrate having shallow trench isolation regions formed within it containing an trench insulator;
• at least one planar MOS transistor formed over said semiconductor substrate in a logic region, the logic region isolated from the embedded memory region by at least one shallow trench isolation region;
• at least one finFET transistor formed on a silicon fin in the embedded memory region, the silicon fin being formed between two adjacent shallow trench isolation regions;
• and
• at least one metal-insulator-metal (MIM) capacitor formed in the memory region above the substrate, the at least one MIM capacitor comprising a first conductive layer, a dielectric layer disposed over the first conductive layer, and a second conductive layer formed over the dielectric layer, and wherein the first conductive layer is coupled to the finFET transistor to form a memory storage cell;
• and
• one or more conductors formed coupling the at least one planar transistor to the at least one memory storage cell to form a circuit.

A semiconductor device, comprising:

• a semiconductor substrate having one or more shallow trench isolation regions formed within it containing an trench insulator;
• a plurality of planar MOS transistors formed over said semiconductor substrate in a logic region, the logic region isolated from an embedded memory region by at least one shallow trench isolation region;
• a first insulating layer formed over the substrate;
• a second insulating layer formed over the substrate;
• and
• a memory array formed in the embedded memory region, comprising:
• plurality of 1 T RAM cells each formed from a finFET transistor having one of a source and drain region coupled to an associated MIM capacitor formed in the second insulating layer;
• at least one word line formed of a conductive material overlying the substrate in the embedded memory region and coupled to the gates of two or more of the finFET transistors of two or more of the 1 T RAM cells;
• and
• at least one bit line formed of a conductive material overlying the substrate in the embedded memory region, isolated from the at least one word line by an insulating layer and coupled to one of the source and drain terminals of two or more of the finFET transistors of two or more of the 1 T RAM cells.