Integrated circuit with buried digit line
AssigneeMicron Technology, Inc.
InventorDavid H. Wells
Life of this patent
Estimating the term…
Abstract
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.
Claims20
An integrated circuit having a memory array, the integrated circuit comprising:
- a trench comprising a first trench wall and a second trench wall substantially parallel to and spaced from the first trench wall;
- a digit line within the trench in contact with the first trench wall, wherein said contact electrically connects the digit line to sources of a plurality of transistors in the memory array;
- and
- an insulating layer within the trench separating the digit line from the second trench wall.
An integrated circuit comprising:
- a trench in a semiconductor material, the trench having a first trench wall and a second trench wall opposite the first trench wall;
- a digit line in the trench, wherein the digit line electrically contacts a transistor active region via the first trench wall;
- and
- an insulating element in the trench, wherein the insulating element separates the digit line from the second trench wall.
Dependencies are inferred from the claim text.