H10B 12/09
With simultaneous manufacture of the peripheral circuit region and memory cells
Official title: {with simultaneous manufacture of the peripheral circuit region and memory cells}
H10B12/09 (With simultaneous manufacture of the peripheral circuit region and memory cells) appears on 2,838 US grants and 3,233 published applications in this corpus.
Search patents in H10B- Granted patents
- 2,838
- Published applications
- 3,233
- Assignees
- 202
- Inventors
- 3,801
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1993 | 1 | 0 |
| 1994 | 3 | 0 |
| 1995 | 3 | 0 |
| 1996 | 1 | 0 |
| 1997 | 3 | 0 |
| 1998 | 10 | 0 |
| 1999 | 30 | 0 |
| 2000 | 94 | 0 |
| 2001 | 155 | 85 |
| 2002 | 171 | 207 |
| 2003 | 180 | 184 |
| 2004 | 192 | 198 |
| 2005 | 131 | 161 |
| 2006 | 127 | 152 |
| 2007 | 95 | 133 |
| 2008 | 88 | 102 |
| 2009 | 108 | 103 |
| 2010 | 106 | 102 |
| 2011 | 83 | 127 |
| 2012 | 91 | 143 |
| 2013 | 114 | 100 |
| 2014 | 116 | 89 |
| 2015 | 98 | 90 |
| 2016 | 73 | 43 |
| 2017 | 51 | 33 |
| 2018 | 44 | 63 |
| 2019 | 70 | 66 |
| 2020 | 60 | 64 |
| 2021 | 63 | 91 |
| 2022 | 70 | 152 |
| 2023 | 90 | 206 |
| 2024 | 106 | 165 |
| 2025 | 118 | 178 |
| 2026 | 93 | 196 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Semiconductor device and method for manufacturing the same29 Sep 2026US 12,749,525 B2Nanya Technology Corporation
- Semiconductor device comprising cell gate conductive layer with top surface at different levels29 Sep 2026US 12,751,003 B2Samsung Electronics Co., Ltd.
- Semiconductor memory device including buried gate pattern15 Sep 2026US 12,740,048 B2Samsung Electronics Co., Ltd.
- Semiconductor device15 Sep 2026US 12,740,055 B2Samsung Electronics Co., Ltd.
- Method of fine pitch pattering for semiconductor device and method of manufacturing the same15 Sep 2026US 12,740,358 B2Samsung Electronics Co., Ltd.
- Semiconductor structure and method of manufacturing the same8 Oct 2026US 2026/0313878 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Stress liner integration in memory devices8 Oct 2026US 2026/0313991 A1Micron Technology, Inc.
- Semiconductor structure and forming method thereof1 Oct 2026US 2026/0304736 A1Swaysure Technology Co., Ltd.
- Semiconductor memory device1 Oct 2026US 2026/0304744 A1Samsung Electronics Co., Ltd.
- Memory Circuitry And Methods Used In Forming Memory Circuitry1 Oct 2026US 2026/0304756 A1Micron Technology, Inc.
Most cited
By later US patents
- Three-dimensional integrated circuit device and its manufacturing method469US 5,998,808 ASony Corporation · 1999
- Method and structure for a 1T-RAM bit cell and macro263US 7,425,740 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2008
- Mixed memory integration with NVRAM, dram and sram cell structures on same substrate229US 6,424,011 B1International Business Machines Corporation · 2002
- Conductive layer buried-type substrate, method of forming the conductive layer buried-type substrate, and method of fabricating semiconductor device using the conductive layer buried-type substrate228US 8,354,308 B2Samsung Electronics Co., Ltd. · 2013
- Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure198US 6,232,173 B1International Business Machines Corporation · 2001