Semiconductor device

A semiconductor device, comprising:

• a lower structure;
• a vertical channel transistor on the lower structure;
• a peripheral semiconductor body on the lower structure;
• a peripheral device isolation region on the lower structure and on a side surface of the peripheral semiconductor body;
• a peripheral gate on an upper surface of the peripheral semiconductor body;
• and
• peripheral source/drain regions in the peripheral semiconductor body on both sides of the peripheral gate,
• wherein the vertical channel transistor includes:
• a lower cell source/drain region disposed in a lower region of a cell semiconductor body;
• an upper cell source/drain region in an upper region of the cell semiconductor body;
• a cell channel region in the cell semiconductor body between the lower cell source/drain region and the upper cell source/drain region;
• a cell gate electrode facing a first side surface of the cell channel region;
• and
• a cell gate dielectric layer between the first side surface of the cell channel region and the cell gate electrode,
• wherein the lower structure includes a lower insulating layer and a bit line electrically connected to the lower cell source/drain region,
• wherein the peripheral device isolation region includes a gap-fill insulating layer and a buffer liner between a side surface of the peripheral semiconductor body and a side surface of the gap-fill insulating layer,
• wherein a lower surface of the gap-fill insulating layer and a lower end portion of the buffer liner are in contact with the lower insulating layer of the lower structure.

A semiconductor device, comprising:

• a lower structure;
• a vertical channel transistor disposed on the lower structure;
• a peripheral semiconductor body disposed on the lower structure, at least a portion of a side surface of the peripheral semiconductor body having a negative slope;
• and
• a peripheral device isolation region on the side surface of the peripheral semiconductor body, on the lower structure,
• wherein the vertical channel transistor includes:
• a lower cell source/drain region in a lower region of a cell semiconductor body;
• an upper cell source/drain region in an upper region of the cell semiconductor body;
• a cell channel region in the cell semiconductor body between the lower cell source/drain region and the upper cell source/drain region;
• a cell gate electrode facing a first side surface of the cell channel region;
• and
• a cell gate dielectric layer between the first side surface of the cell channel region and the cell gate electrode,
• wherein the lower structure includes:
• a bit line electrically connected to the lower cell source/drain region of the vertical channel transistor;
• and
• a shield structure including a line portion disposed between the bit line and an adjacent bit line,
• wherein the peripheral device isolation region includes:
• a gap-fill insulating layer;
• and
• an insulating liner between the side surface of the peripheral semiconductor body and a side surface of the gap-fill insulating layer,
• wherein an upper end portion of the peripheral semiconductor body is at a first height level,
• a lower end portion of the peripheral semiconductor body is at a second height level,
• an upper end portion of the insulating liner is at a third height level, and
• a lower end portion of the insulating liner is at a fourth height level,
• wherein a first difference between the first height level and the third height level is different from a second difference between the second height level and the fourth height level.