Method of fine pitch pattering for semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device, the method comprising:

• forming a plurality of reference patterns and a peripheral pattern on a feature layer such that the peripheral pattern is connected to end portions of the plurality of reference patterns;
• forming a plurality of first spacers on both sidewalls of each of the plurality of reference patterns;
• removing the plurality of reference patterns;
• forming a plurality of second spacers on opposite sidewalls of each of the plurality of first spacers;
• forming a gap-fill insulation layer on the feature layer such that the gap-fill insulation layer fills a space between the plurality of second spacers and contacts the feature layer;
• removing the gap-fill insulation layer and the plurality of first spacers such that the plurality of second spacers and the peripheral pattern remain on the feature layer;
• and
• patterning the feature layer using the plurality of second spacers and the peripheral pattern as an etch mask.

A method of manufacturing a semiconductor device, the method comprising:

• providing a substrate including a cell array region and a boundary region;
• forming a feature layer on the substrate;
• forming a plurality of reference patterns and a peripheral pattern on the feature layer using a first material, the plurality of reference patterns being on the cell array region, and the peripheral pattern being connected to end portions of the plurality of reference patterns and on the boundary region;
• forming a plurality of first spacers on opposite sidewalls of each of the plurality of reference patterns using a second material;
• removing the plurality of reference patterns;
• forming a plurality of second spacers on opposite sidewalls of each of the plurality of first spacers by using the first material, wherein the feature layer is exposed between neighboring pairs of first spacers of the plurality of first spacers;
• forming a gap-fill insulation layer to cover the feature layer, the plurality of first spacers, and the plurality of second spacers, the gap-fill insulation layer contacting the feature layer;
• removing the plurality of first spacers and the gap-fill insulation layer such that the plurality of second spacers and the peripheral pattern remain on the feature layer with the feature layer exposed between neighboring pairs of second spacers of the plurality of second spacers;
• patterning the feature layer using the plurality of second spacers and the peripheral pattern as an etch mask;
• and
• removing a portion of the substrate using the feature layer as an etch mask to form a device isolation trench.