Semiconductor device comprising cell gate conductive layer with top surface at different levels

A semiconductor device, comprising:

• a substrate including a first cell active pattern and a dummy active pattern;
• a cell gate dielectric layer on the first cell active pattern and the dummy active pattern;
• a cell gate conductive layer on the cell gate dielectric layer;
• and
• a bit-line structure electrically connected to the first cell active pattern,
• wherein the cell gate conductive layer includes
• a dummy overlap section overlapping the dummy active pattern, and
• a cell overlap section overlapping the first cell active pattern, and
• wherein a maximum thickness of the dummy overlap section is greater than a maximum thickness of the cell overlap section, and
• wherein a top surface of the dummy overlap section is at a level higher than a level of a top surface of the cell overlap section.

A semiconductor device, comprising:

• a substrate including a first cell active pattern, a second cell active pattern, and a dummy active pattern;
• a cell gate dielectric layer on the first cell active pattern, the second cell active pattern, and the dummy active pattern;
• a first cell gate conductive layer on the cell gate dielectric layer;
• a second cell gate conductive layer on the first cell gate conductive layer;
• a cell gate capping layer on the first cell gate conductive layer and the second cell gate conductive layer;
• a dielectric pattern on the cell gate capping layer;
• a bit-line structure on the dielectric pattern;
• a node contact on the first cell active pattern;
• a landing pad on the node contact;
• and
• a data storage pattern electrically connected to the landing pad,
• wherein the first cell gate conductive layer includes
• a first top surface in contact with the second cell gate conductive layer, and
• a second top surface in contact with the cell gate capping layer, and
• wherein the first top surface is at a level lower than a level of the second top surface.