Semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsDonghyun Jang, Giduck Kweon, Dongchan Kim, Jin Sung Kim, Jisu Byun, Dongwook Seo, Dong Min Sim, Wonseok Yoo, Namhoon Lee
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Abstract
The present invention provides a semiconductor memory device. A semiconductor memory device includes a lower insulating layer, back-gate lines each extending in a first direction on the lower insulating layer, first semiconductor patterns on first side surfaces of the back-gate lines, and second semiconductor patterns on second side surfaces of the back gate lines. The first semiconductor patterns and the second semiconductor patterns are alternately disposed along the first direction.
Claims20
A semiconductor memory device comprising:
- a lower insulating layer;
- back-gate lines each extending in a first direction on the lower insulating layer;
- first semiconductor patterns on first side surfaces of the back-gate lines;
- and
- second semiconductor patterns on second side surfaces of the back-gate lines,
- wherein the first semiconductor patterns and the second semiconductor patterns are alternately disposed along the first direction.
A semiconductor memory device comprising:
- a lower insulating layer;
- a back-gate line extending in a first direction on the lower insulating layer;
- a first gate line on a first side surface of the back-gate line;
- a second gate line on a second side surface of the back-gate line;
- first semiconductor patterns between the back-gate line and the first gate line;
- and
- second semiconductor patterns between the back-gate line and the second gate line,
- wherein the first semiconductor patterns and the second semiconductor patterns are offset in the first direction.
A semiconductor memory device comprising:
- a peripheral circuit structure including peripheral circuits on a substrate;
- and
- a cell structure electrically connected to the peripheral circuit structure,
- wherein the cell structure comprises:
- a lower insulating layer;
- bit lines in the lower insulating layer;
- a back-gate line extending in a first direction on the lower insulating layer;
- a first gate line and a second gate line spaced apart from one another with the back-gate line therebetween;
- first semiconductor patterns between the back-gate line and the first gate line;
- second semiconductor patterns between the back-gate line and the second gate line;
- and
- data storage patterns on the first semiconductor patterns and the second semiconductor patterns,
- wherein the first semiconductor patterns and the second semiconductor patterns are arranged in a shape of zigzag in a plan view.
Dependencies are inferred from the claim text.