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US 2026/0304736 A1Published application
Semiconductor structure and forming method thereof
AssigneeSwaysure Technology Co., Ltd.
InventorsJun Xia, Kuo-Wen Lai, Yichuan Wang
Life of this patent
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Abstract
PROBLEM TO BE SOLVED: To provide a semiconductor device with high reliability and high degree of integration at low cost. SOLUTION: The semiconductor device includes: a substrate including a first region MC and a second region PC around the first region; an insulating film that is formed on the second region PC; electrodes that are formed on the substrate 1 in the first region MC; a dielectric film that is formed on the electrodes; and counter electrodes that are formed on the dielectric film. Shape of side-walls of the insulating film includes part that reflects peripheral shape of the side-walls of the counter electrodes.
Claims14
A semiconductor structure, comprising:
- a substrate structure, wherein the substrate structure has a capacitor region and a logic region adjacent to the capacitor region, the capacitor region and the logic region are used as a capacitor cell array region, and the substrate structure comprises a first insulation layer and a plurality of conductive portions inlaid at intervals in the first insulation layer, wherein the conductive portions are located in the capacitor region, and a top surface of the conductive portion is exposed from the first insulation layer;
- a first etching stop layer, located in the capacitor region and at least covering a top portion of the conductive portion;
- a second etching stop layer, located in the logic region and covering a top portion of the first insulation layer, wherein the second etching stop layer and the first etching stop layer are located in a same layer, and top surfaces of the second etching stop layer and the first etching stop layer are flush;
- a first stacked structure, covering a layer in which the first etching stop layer and the second etching stop layer are located;
- a plurality of first electrode columns, wherein each first electrode column extends through the first stacked structure and the first etching stop layer and is in contact with and connected to a corresponding one of the conductive portions;
- and
- a slit opening, extending through the first stacked structure exposing the second etching stop layer;
- wherein
- the first etching stop layer and the second etching stop layer are made of a same material, and the first etching stop layer and the second etching stop layer are separated by a protective layer such that the protective layer protects a side wall of the first etching stop layer in a process of performing pickling on a first stacked structure through the slit opening;
- or the first etching stop layer and the second etching stop layer are made of different materials, and a contact interface is formed between the first etching stop layer and the second etching stop layer such that the second etching stop layer protects a side wall of the first etching stop layer in a process of performing pickling on a first stacked structure through the slit opening.
7 more elements
A semiconductor structure forming method, comprising:
- providing a substrate structure, wherein the substrate structure has a capacitor region and a logic region adjacent to the capacitor region, the capacitor region and the logic region are used as a capacitor cell array region, and substrate structure comprises a first insulation layer and a plurality of conductive portions inlaid at intervals in the first insulation layer, the conductive portions are located in the capacitor region, and a top surface of the conductive portion is exposed from the first insulation layer;
- forming an etching stop structure on the substrate structure, wherein the etching stop structure comprises:
- a first etching stop layer, located in the capacitor region and at least covering a top portion of the conductive portion;
- and
- a second etching stop layer, located in the logic region and covering a top portion of the first insulation layer, wherein the first etching stop layer and the second etching stop layer are located in a same layer, and top surfaces of the first etching stop layer and the second etching stop layer are flush;
- forming a first stacked structure on the etching stop structure;
- forming a plurality of first electrode column accommodating holes extending through the first stacked structure, wherein the first electrode column accommodating hole exposes the conductive portion;
- preparing a first electrode column in the first electrode column accommodating hole, wherein each of the first electrode columns is in contact with and connected to a corresponding one of the conductive portions;
- and
- forming a slit opening extending through the first stacked structure, wherein the second etching stop layer is exposed from the slit opening;
- wherein
- the first etching stop layer and the second etching stop layer are made of a same material, and the first etching stop layer and the second etching stop layer are separated by a protective layer such that the protective layer protects a side wall of the first etching stop layer in a process of performing pickling on a first stacked structure through the slit opening;
- or the first etching stop layer and the second etching stop layer are made of different materials, and a contact interface is formed between the first etching stop layer and the second etching stop layer such that the second etching stop layer protects a side wall of the first etching stop layer in a process of performing pickling on a first stacked structure through the slit opening.
10 more elements
Dependencies are inferred from the claim text.