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US 12,740,048 B2Granted
Semiconductor memory device including buried gate pattern
AssigneeSamsung Electronics Co., Ltd.
InventorsChan-Sic Yoon, Kiseok Lee
Life of this patent
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Abstract
A semiconductor device includes a substrate having an active region and a gate structure crossing the active region. The gate structure may include a gate pattern penetrating an upper portion of the active region in a first direction perpendicular to a bottom surface of the substrate, a metal-containing pattern on the gate pattern, and a barrier pattern interposed between the gate pattern and the metal-containing pattern and extended to face opposite side surfaces of the metal-containing pattern.
Claims20
A semiconductor device, comprising:
- a substrate including an active region;
- a gate structure crossing the active region, the gate structure including:
- a gate pattern penetrating an upper portion of the active region in a first direction perpendicular to a bottom surface of the substrate,
- a metal-containing pattern on the gate pattern disposed at a first height above the bottom surface of the substrate and disposed so that in the first direction, the gate pattern is between the active region of the substrate and the metal-containing pattern, the metal-containing pattern including a bottom surface facing the gate pattern and opposite side surfaces extending from the bottom surface away from the gate pattern,
- a barrier pattern between the gate pattern and the metal-containing pattern, the barrier pattern formed of a nitride and extending along the opposite side surfaces of the metal-containing pattern,
- wherein the gate pattern is disposed both above and below a topmost surface of the active region, and
- a gate insulating pattern between a bottom surface of the gate pattern and the substrate, the gate insulating pattern additionally extending along opposite side surfaces of the gate pattern, and formed of a continuous material extending continuously from the bottom surface of the gate pattern to the first height to overlap the metal-containing pattern in a second direction parallel to the bottom surface of the substrate;
- and
- a pair of impurity regions disposed adjacent to opposite side surfaces of the gate structure such that the gate structure is at a height above a topmost portion of each impurity region and is at a height below a bottommost portion of each impurity region.
6 more elements
A semiconductor device, comprising:
- a substrate including active regions;
- a first gate structure and a second gate structure crossing the active regions, respectively, each of the first gate structure and the second gate structure including:
- a gate pattern penetrating an upper portion of a corresponding active region, a metal-containing pattern on the gate pattern, so that each gate pattern is between a respective active region and a respective metal-containing pattern in a first direction perpendicular to a bottom surface of the substrate, and a barrier pattern between the gate pattern and the metal-containing pattern in the first direction, wherein for each metal-containing pattern, the barrier pattern additionally extends along opposite side surfaces of the metal-containing pattern;
- a buried semiconductor pattern between the substrate and the second gate structure,
- wherein each gate pattern is disposed both above and below a topmost surface of the active regions;
- a first gate insulating pattern between the first gate structure and the substrate and additionally extending along opposite side surfaces of the gate pattern of the first gate structure and along side surfaces of the metal-containing pattern of the first gate structure, wherein the first gate insulating pattern is disposed to overlap each of a respective active region and a respective metal-containing pattern in a second direction parallel to the bottom surface of the substrate, and has the same thickness in the second direction where it overlaps the respective active region as where it overlaps the respective metal-containing pattern;
- and
- for each of the first gate structure and the second gate structure, a pair of impurity regions disposed adjacent to opposite side surfaces of the gate structure, such that each gate structure is at a height above a topmost portion of each impurity region and is at a height below a bottommost portion of each impurity region.
5 more elements
A semiconductor device, comprising:
- a substrate including active regions;
- a first gate structure and a second gate structure crossing the active regions, respectively, wherein:
- the first gate structure includes:
- a gate pattern penetrating an upper portion of a first active region of the active regions,
- a metal-containing pattern on the gate pattern so that the gate pattern is between the metal-containing pattern and the substrate, and
- a barrier pattern between the gate pattern and the metal-containing pattern, the barrier pattern extending along opposite side surfaces of the metal-containing pattern, and
- the second gate structure includes a horizontal gate pattern, a horizontal barrier pattern, and a horizontal metal-containing pattern, which are sequentially stacked on a top surface of another of the active regions such that none of the horizontal gate pattern, the horizontal barrier pattern, or the horizontal metal-containing pattern penetrates the active regions, and does not include a gate pattern penetrating an upper portion of any of the active regions,
- wherein each gate pattern of the first gate structure is disposed both above and below a topmost surface of the active regions;
- and
- a pair of impurity regions disposed adjacent to opposite side surfaces of the first gate structure such that the first gate structure is at a height above a topmost portion of each impurity region and is at a height below a bottommost portion of each impurity region.
7 more elements
Dependencies are inferred from the claim text.