US 2026/0313991 A1 · STRESS LINER INTEGRATION IN MEMORY DEVICES

Abstract

A variety of applications can include an electronic device having one or more memory devices that include transistors in a periphery to a memory array of the memory device, where one or more of the transistors includes a stress liner near channel structures of the one or more transistors, while other transistors in the periphery do not have a stress liner near their channel structures. The stress liner can be formed after transistors have been formed in the periphery and memory cells have been formed in the memory array and before contacts to the transistors have been patterned. The transistors for which a stress liner is being formed can be uncovered, while maintaining the transistors without a stress liner covered. Transistors having an associated stress liner can be n-type transistors with a tensile stress liner or p-type transistors with a compressive stress liner.

Claims20

Dependent claims

A memory device comprising:

an array of memory cells;
a transistor in a periphery to the array, the transistor including a gate stack;
a dielectric cap on top of the gate stack;
a dielectric sidewall vertically along the gate stack;
a stress liner on the dielectric cap and on the dielectric sidewall;
and
an interlayer dielectric on the stress liner on the dielectric cap, the interlayer dielectric
extending into the array.

5 more elements

A method of forming a memory die, the method comprising:

forming memory cells of an array and forming a transistor in a periphery to the array in an integrated process, including forming an interlayer dielectric above the transistor extending into the array;
forming, through the interlayer dielectric, an opening to a cap to a gate stack of the transistor and to a sidewall to the gate stack;
forming, via the opening, a stress liner on and contacting the cap to the transistor and sidewall to the transistor;
and
forming, through the stress liner, contacts to the transistor.

2 more elements

Dependencies are inferred from the claim text.

Stress liner integration in memory devices

Life of this patent

Stress liner integration in memory devices

Life of this patent

Abstract

Claims20