H10B 12/053
The transistor being at least partially in a trench in the substrate
Official title: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
H10B12/053 (The transistor being at least partially in a trench in the substrate) appears on 2,506 US grants and 3,223 published applications in this corpus.
Search patents in H10B- Granted patents
- 2,506
- Published applications
- 3,223
- Assignees
- 177
- Inventors
- 3,048
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 2 | 0 |
| 1993 | 2 | 0 |
| 1994 | 2 | 0 |
| 1995 | 3 | 0 |
| 1996 | 3 | 0 |
| 1997 | 1 | 0 |
| 1998 | 5 | 0 |
| 1999 | 7 | 0 |
| 2000 | 21 | 0 |
| 2001 | 29 | 16 |
| 2002 | 41 | 38 |
| 2003 | 45 | 43 |
| 2004 | 49 | 50 |
| 2005 | 38 | 74 |
| 2006 | 42 | 101 |
| 2007 | 56 | 112 |
| 2008 | 65 | 107 |
| 2009 | 85 | 137 |
| 2010 | 116 | 113 |
| 2011 | 113 | 151 |
| 2012 | 117 | 198 |
| 2013 | 156 | 148 |
| 2014 | 149 | 112 |
| 2015 | 119 | 124 |
| 2016 | 114 | 88 |
| 2017 | 76 | 51 |
| 2018 | 65 | 83 |
| 2019 | 91 | 108 |
| 2020 | 86 | 106 |
| 2021 | 106 | 169 |
| 2022 | 119 | 186 |
| 2023 | 134 | 282 |
| 2024 | 137 | 271 |
| 2025 | 180 | 188 |
| 2026 | 125 | 167 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Memory cell with reduced parasitic capacitance and conductive via extending into source/drain region6 Oct 2026US 12,757,383 B2Nanya Technology Corporation
- Memory cell with reduced parasitic capacitance and spacer between u-shaped liner and air gap6 Oct 2026US 12,757,384 B2Nanya Technology Corporation
- Semiconductor device and manufacturing method thereof6 Oct 2026US 12,757,387 B2Nanya Technology Corporation
- Semiconductor device and method for forming the same22 Sep 2026US 12,745,385 B2SK hynix Inc.
- Semiconductor apparatus having multi-layered bit line contact and manufacturing method of the same22 Sep 2026US 12,745,386 B2Samsung Electronics Co., Ltd.
- Memory device and method for forming the same1 Oct 2026US 2026/0304742 A1Nanya Technology Corporation
- Memory device and methods of fabricating the same24 Sep 2026US 2026/0293117 A1Nanya Technology Corporation
- Memory devices having vertical transistors and fabricating methods thereof17 Sep 2026US 2026/0282330 A1Yangtze Memory Technologies Co., Ltd.
- Recess gate and interconnector structure and method for preparing the same17 Sep 2026US 2026/0282336 A1Nanya Technology Corporation
- Recess gate and interconnector structure and method for preparing the same17 Sep 2026US 2026/0282337 A1Nanya Technology Corporation
Most cited
By later US patents
- Memory cell having a vertical transistor with buried source/drain and dual gates325US 6,150,687 AMicron Technology, Inc. · 2000
- Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region290US 6,686,624 B2Monolithic System Technology, Inc. · 2004
- 4 F2 folded bit line DRAM cell structure having buried bit and word lines285US 6,689,660 B1Micron Technology, Inc. · 2004
- Integrated circuit with buried digit line264US 8,102,008 B2Micron Technology, Inc. · 2012
- Reverse construction memory cell263US 7,776,715 B2Micron Technology, Inc. · 2010