Reverse construction memory cell
AssigneeMicron Technology, Inc.
InventorsDavid H. Wells, H. Montgomery Manning
Life of this patent
Estimating the term…
Abstract
A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
Claims20
A method of fabricating a memory array, the method comprising:
- forming at least three vertically stacked doped semiconductor layers of alternating conductivity type on a carrier substrate;
- forming a plurality of digit lines for the memory array separated by an insulating material, wherein the digit lines are arrayed over the vertically stacked doped semiconductor layers on the carrier substrate;
- bonding at least a portion of a structure formed on the carrier substrate to a host substrate, wherein the structure comprises the vertically stacked doped semiconductor layers and the plurality of digit lines;
- and
- separating a portion of the carrier substrate from the host substrate while leaving the structure on the host substrate.
A method comprising:
- forming a plurality of at least partially fabricated vertical transistor structures on a carrier substrate;
- forming a plurality of digit lines over the at least partially fabricated vertical transistor structures;
- separating the digit lines and the at least partially fabricated vertical transistor structures from the carrier substrate;
- bonding the digit lines and the at least partially fabricated vertical transistor structures to a host substrate, such that the digit lines are positioned between the host substrate and the at least partially fabricated vertical transistor structures.
Dependencies are inferred from the claim text.