Recess gate and interconnector structure and method for preparing the same

Abstract

The present application provides a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate having an active region; a recess gate structure disposed in the substrate and intersecting the active region; a bit line contact including a polysilicon stack and disposed on the substrate; a conductive pillar disposed over the substrate and electrically connected to the active region; a landing pad disposed on the conductive pillar and electrically connected to the conductive pillar; and a stack of dielectric layers disposed over the substrate and laterally surrounding the bit line contact. The polysilicon stack includes a first polysilicon layer and a second polysilicon layer disposed over the first polysilicon layer. The second polysilicon layer is in direct contact with the stack of dielectric layers.

Dependencies are inferred from the claim text.