G01R 31/31858
Delay testing
Official title: {Delay testing}
G01R31/31858 (Delay testing) appears on 197 US grants and 138 published applications in this corpus.
Search patents in G01R- Granted patents
- 197
- Published applications
- 138
- Assignees
- 89
- Inventors
- 401
- Latest grant
- 16 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 2 | 0 |
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 1 | 0 |
| 1991 | 4 | 0 |
| 1992 | 1 | 0 |
| 1993 | 3 | 0 |
| 1994 | 4 | 0 |
| 1995 | 3 | 0 |
| 1996 | 6 | 0 |
| 1997 | 8 | 0 |
| 1998 | 8 | 0 |
| 1999 | 7 | 0 |
| 2000 | 7 | 0 |
| 2001 | 5 | 1 |
| 2002 | 10 | 11 |
| 2003 | 7 | 11 |
| 2004 | 6 | 7 |
| 2005 | 9 | 13 |
| 2006 | 8 | 13 |
| 2007 | 6 | 7 |
| 2008 | 13 | 9 |
| 2009 | 7 | 12 |
| 2010 | 8 | 3 |
| 2011 | 16 | 14 |
| 2012 | 6 | 2 |
| 2013 | 5 | 5 |
| 2014 | 5 | 3 |
| 2015 | 5 | 2 |
| 2016 | 3 | 3 |
| 2017 | 2 | 2 |
| 2018 | 2 | 2 |
| 2019 | 2 | 2 |
| 2020 | 2 | 2 |
| 2021 | 2 | 1 |
| 2022 | 1 | 3 |
| 2023 | 4 | 3 |
| 2024 | 4 | 2 |
| 2025 | 1 | 4 |
| 2026 | 1 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Characterizing path margin monitors without the use of scan chains16 Jun 2026US 12,656,391 B2Synopsys, Inc.
- Test pattern generation using multiple scan enables1 Jul 2025US 12,345,764 B2STMicroelectronics International N. V.
- Multiplexer for SDFQ having differently-sized scan and data transistors, semiconductor device including same and methods of manufacturing same24 Sep 2024US 12,099,090 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Using scan chains to read out data from integrated sensors during scan tests5 Mar 2024US 11,921,160 B2Synopsys, Inc.
- Core and interface scan testing architecture and methodology23 Jan 2024US 11,879,942 B1Micron Technology, Inc.
- Test pattern generating method and device1 Jan 2026US 2026/0002991 A1Samsung Electronics Co., Ltd.
- Critical path sensitization in electronic systems30 Oct 2025US 2025/0334635 A1NXP B. V.
- Monitor block, interface circuit, and method of operating debugging system31 Jul 2025US 2025/0244385 A1Samsung Electronics Co., Ltd.
- Characterizing path margin monitors without the use of scan chains22 May 2025US 2025/0164550 A1Synopsys, Inc.
- Scan-shift buffer isolator for dynamic power reduction30 Jan 2025US 2025/0035703 A1STMicroelectronics International N. V.
Most cited
By later US patents
- Multiple clock rate test apparatus for testing digital systems134US 5,349,587 ANorthern Telecom Limited · 1994
- Method and apparatus for testing circuits with multiple clocks117US 6,442,722 B1LogicVision, Inc. · 2002
- Bist architecture for measurement of integrated circuit delays95US 5,923,676 ALogic Vision, Inc. · 1999
- Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation91US 5,889,788 AMotorola, Inc. · 1999
- Scan based testing of an integrated circuit for compliance with timing specifications90US 5,812,561 AMotorola, Inc. · 1998