US 11,879,942 B1Granted

Core and interface scan testing architecture and methodology

AssigneeMicron Technology, Inc.

InventorsBanadappa Shivaray, Shrikrishna Pundoor, Mahesh Rawal, Aviral Agarwal

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Abstract

Implementations described herein relate to a core and interface scan testing. In some implementations, an integrated circuit may include input scan flip-flops (ISFFs) arranged in multiple ISFF stages that include a first ISFF stage and a second ISFF stage. Inputs to the first ISFF stage are connected to inputs of the integrated circuit. Inputs to the second ISFF stage are connected to outputs of a logic component that is connected to outputs of the first ISFF stage. The integrated circuit may include output scan flip-flops (OSFFS) arranged in multiple OSFF stages that include a first OSFF stage and a second OSFF stage. Outputs from the first OSFF stage are connected to outputs of the integrated circuit. Outputs from the second OSFF stage are connected to inputs of a logic component that is connected to inputs of the first OSFF stage. The integrated circuit may include core scan flip flops.

Claims25

Dependent claims

An integrated circuit, comprising:

a plurality of input scan flip-flops arranged in a plurality of input scan flip-flop stages that includes at least a first input scan flip-flop stage and a second input scan flip-flop stage,
wherein inputs to a first plurality of input scan flip-flops included in the first input scan flip-flop stage are connected to inputs of the integrated circuit, and
wherein inputs to a second plurality of input scan flip-flops included in the second input scan flip-flop stage are connected to outputs of a logic component that is connected to outputs of the first plurality of input scan flip-flops;
and
a plurality of output scan flip-flops arranged in a plurality of output scan flip-flop stages that includes at least a first output scan flip-flop stage and a second output scan flip-flop stage,
wherein outputs from a first plurality of output scan flip-flops included in the first output scan flip-flop stage are connected to outputs of the integrated circuit, and
wherein outputs from a second plurality of output scan flip-flops included in the second output scan flip-flop stage are connected to inputs of a logic component that is connected to inputs of the first plurality of output scan flip-flops.

4 more elements

A system, comprising:

a plurality of integrated circuits, wherein each integrated circuit, included in the plurality of integrated circuits, includes:
a plurality of lower-level input scan flip-flops arranged in a plurality of lower-level input scan flip-flop stages that includes at least a first lower-level input scan flip-flop stage and a second lower-level input scan flip-flop stage,
wherein inputs to a first plurality of lower-level input scan flip-flops included in the first lower-level input scan flip-flop stage are connected to inputs of a corresponding integrated circuit, of the plurality of integrated circuits, that includes the plurality of lower-level input scan flip-flops, and
wherein inputs to a second plurality of lower-level input scan flip-flops included in the second lower-level input scan flip-flop stage are connected to outputs of a logic component that is connected to outputs of the first plurality of lower-level input scan flip-flops;
a plurality of lower-level output scan flip-flops arranged in a plurality of lower-level output scan flip-flop stages that includes at least a first lower-level output scan flip-flop stage and a second lower-level output scan flip-flop stage,
wherein outputs from a first plurality of lower-level output scan flip-flops included in the first lower-level output scan flip-flop stage are connected to outputs of the corresponding integrated circuit, and
wherein outputs from a second plurality of lower-level output scan flip-flops included in the second lower-level output scan flip-flop stage are connected to inputs of a logic component that is connected to inputs of the first plurality of lower-level output scan flip-flops;
and
a plurality of lower-level core scan flip-flops,
wherein a first stage of lower-level core scan flip-flops, included in the plurality of lower-level core scan flip-flops, are connected to a final lower-level input scan flip-flop stage of the plurality of lower-level input scan flip-flop stages, and
wherein a second stage of lower-level core scan flip-flops, included in the plurality of lower-level core scan flip-flops, are connected to an initial lower-level output scan flip-flop stage of the plurality of lower-level output scan flip-flop stages.

8 more elements

A method, comprising:

loading test data into at least one of:
a plurality of input scan flip-flops of a first integrated circuit, wherein the plurality of input scan flip-flops are arranged in a plurality of input scan flip-flop stages,
a plurality of output scan flip-flops of the first integrated circuit, wherein the plurality of output scan flip-flops are arranged in a plurality of output scan flip-flop stages, or
a plurality of core scan flip-flops of the first integrated circuit,
wherein a first stage of core scan flip-flops, included in the plurality of core scan flip-flops, are connected to a final input scan flip-flop stage of the plurality of input scan flip-flop stages, and
wherein a second stage of core scan flip-flops, included in the plurality of core scan flip-flops, are connected to an initial output scan flip-flop stage of the plurality of output scan flip-flop stages;
executing a test associated with the first integrated circuit based on loading the test data into at least one of the plurality of input scan flip-flops, the plurality of output scan flip-flops, or the plurality of core scan flip-flops;
and
obtaining test results of executing the test.

6 more elements

A method, comprising:

loading, by a system that includes a first integrated circuit and a second integrated circuit, test data into at least one of:
a plurality of lower-level input scan flip-flops of the first integrated circuit, wherein the plurality of lower-level input scan flip-flops of the first integrated circuit are arranged in a plurality of stages,
a plurality of lower-level output scan flip-flops of the first integrated circuit, wherein the plurality of lower-level output scan flip-flops of the first integrated circuit are arranged in a plurality of stages,
a plurality of lower-level core scan flip-flops of the first integrated circuit,
a plurality of lower-level input scan flip-flops of the second integrated circuit, wherein the plurality of lower-level input scan flip-flops of the second integrated circuit are arranged in a plurality of stages,
a plurality of lower-level output scan flip-flops of the second integrated circuit, wherein the plurality of lower-level output scan flip-flops of the second integrated circuit are arranged in a plurality of stages,
a plurality of lower-level core scan flip-flops of the second integrated circuit,
a first plurality of upper-level output scan flip-flops of the system, wherein the first plurality of upper-level output scan flip-flops are arranged in a plurality of stages that includes a final stage that is connected to inputs of the first integrated circuit,
a first plurality of upper-level input scan flip-flops of the system, wherein the first plurality of upper-level input scan flip-flops are arranged in a plurality of stages that includes an initial stage that is connected to outputs of the first integrated circuit,
a second plurality of upper-level output scan flip-flops of the system, wherein the second plurality of upper-level output scan flip-flops are arranged in a plurality of stages that includes a final stage that is connected to inputs of the second integrated circuit,
a second plurality of upper-level input scan flip-flops of the system, wherein the second plurality of upper-level input scan flip-flops are arranged in a plurality of stages that includes an initial stage that is connected to outputs of the second integrated circuit, or
a plurality of upper-level core scan flip-flops of the system;
and
executing, by the system, a test based on loading the test data into at least one of the plurality of lower-level input scan flip-flops of the first integrated circuit, the plurality of lower-level output scan flip-flops of the first integrated circuit, the plurality of lower-level core scan flip-flops of the first integrated circuit, the plurality of lower-level input scan flip-flops of the second integrated circuit, the plurality of lower-level output scan flip-flops of the second integrated circuit, the plurality of lower-level core scan flip-flops of the second integrated circuit, the first plurality of upper-level output scan flip-flops of the system, the first plurality of upper-level input scan flip-flops of the system, the second plurality of upper-level output scan flip-flops of the system, the second plurality of upper-level input scan flip-flops of the system, or the plurality of upper-level core scan flip-flops of the system;
and
obtaining, by the system, test results based on executing the test.

13 more elements

Dependencies are inferred from the claim text.