Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation

An embedded core for use within an integrated circuit, the embedded core comprising:

• a data processor portion coupled to a system clock;
• and
• a plurality of speed path test cells coupled to the data processor portion to enable speed path testing of the data processor portion, wherein each speed path test cell within the plurality of speed path test cells comprises:
• a multiplexor having an output coupled to an input of the data processor portion, a first input coupled to receive normal mode data, and a second input for receiving speed path testing data;
• a first storage element having an output coupled to the second input of the multiplexor, a data input, and a clock input for receiving a test clock that is different from the system clock;
• and
• a second storage element having an output coupled to the data input of the first storage element, a serial data input for receiving serial scan data, and a clock input for receiving a test clock that is different from the system clock, whereby the plurality of speed path test cells provide a logic transition to a circuit path within the data processor portion to test a signal propagation time through the circuit path.

An embedded core for use within an integrated circuit, the embedded core comprising:

• a data processor portion coupled to a system clock;
• and
• a plurality of speed path test cells coupled to the data processor portion to enable speed path testing of the data processor portion, wherein each speed path test cell within the plurality of speed path test cells comprises:
• a first multiplexor having an output, a first input coupled to receive normal mode data from an output of the data processor portion, and a second input;
• a first storage element having an output coupled to the second input of the first multiplexor, a data input, and a clock input for receiving a test clock that is different from the system clock;
• and
• a second storage element having an output coupled to the data input of the first storage element, a serial data input for receiving serial scan data, and a clock input for receiving a test clock that is different from the system clock, whereby the plurality of speed path test cells perform a capture operation for data provided from an output of the data processor portion so that a circuit path within the data processor portion is speed path tested.

An embedded core for use within an integrated circuit, the embedded core comprising:

• a data processor portion coupled to a system clock;
• and
• a plurality of speed path test cells coupled to the data processor portion to enable speed path testing of the data processor portion, wherein each speed path test cell within the plurality of speed path test cells comprises:
• a multiplexor having an output coupled to the data processor portion, a first input coupled to receive normal mode data from an output of the data processor portion, and a second input for receiving speed path testing data;
• a first storage element having an output coupled to the second input of the multiplexor, a data input, and a clock input for receiving a test clock that is different from the system clock;
• a second storage element having an output coupled to the data input of the first storage element, a serial data input for receiving serial scan data, and a clock input for receiving a test clock that is different from the system clock;
• and
• a second multiplexor having an output, a first input coupled to an output of the data processor portion, and a second input coupled to the output of the first storage element.

An integrated circuit comprising:

• an embedded core for executing computer instructions at an operational clock period defined by a system clock;
• logic within the integrated circuit and coupled to the embedded core;
• and
• a plurality of speed path testing cells coupled to the embedded core wherein the plurality of speed path testing cells are coupled to a test clock whereby the system clock initiates a function of either a speed path transition launch or a speed path data capture and the test clock initiates a function opposite of the function enabled by the system clock so that a circuit path within the integrated circuit is speed path tested.

A method for speed path testing an embedded core within an integrated circuit, the method comprising the steps of:

• providing the integrated circuit, the integrated circuit containing the embedded core and microcontroller logic coupled to the embedded core, the integrated circuit containing a plurality of speed path test cells coupled to the embedded core;
• serially shifting data into at least one scan chain within the embedded core;
• serially shifting data into a test scan chain which serially couples each speed path test cell in the plurality of speed path test cells, the step of serially shifting data into the test scan chain being performed in parallel with the step of serially shifting data into the at least one scan chain;
• and
• speed path testing the embedded core using test data provided from the test scan chain.

A method for speed path testing an embedded core within an integrated circuit, the method comprising the steps of:

• providing the integrated circuit, the integrated circuit containing the embedded core and microcontroller logic coupled to the embedded core, the integrated circuit containing a plurality of speed path test cells coupled to the embedded core;
• serially shifting data into at least one scan chain within the embedded core;
• serially shifting data into a test scan chain which serially couples each speed path test cell in the plurality of speed path test cells, the step of serially shifting data into the test scan chain being performed in parallel with the step of serially shifting data into the at least one scan chain;
• and
• speed path testing the embedded core by capturing test data within the test scan chain wherein the test data is provided as output from the embedded core.