Test pattern generation using multiple scan enables

An integrated circuit comprising:

• a circuit under test comprising initiator logic elements and target logic elements;
• a first scan chain of scan flip flops comprising the initiator logic elements, each scan flip flop of the first scan chain comprising a scan enable input coupled to a first scan enable signal;
• a second scan chain of scan flip flops comprising the target logic elements, each of the scan flip flops of the second scan chain comprising a scan enable input coupled to a second scan enable signal;
• and
• a controller configured to test the circuit under test by
• shifting a first test pattern into the first scan chain while both the initiator logic elements and the target logic elements are simultaneously operating in launch mode,
• launching the first test pattern, and
• capturing results from the second scan chain while the initiator logic elements are operating in launch mode simultaneously with the target logic elements operating in capture mode.

A method of testing an integrated circuit, the method comprising:

• shifting a first test pattern into a first set of scan flip flops of the integrated circuit upstream of first logic elements of the integrated circuit while simultaneously asserting both a first scan enable signal and a second scan enable signal, each of the scan flip flops of the first set comprising a scan enable input coupled to the first scan enable signal;
• deasserting the second scan enable signal while continuing to assert the first scan enable signal;
• launching the first test pattern;
• and
• capturing results from a second set of scan flip flops of the integrated circuit downstream of the first logic elements while the first scan enable signal is asserted simultaneously with the second scan enable signal being deasserted, each of the scan flip flops of the second set comprising a scan enable input coupled to the second scan enable signal.