Critical path sensitization in electronic systems

An electronic system, comprising:

• a critical logic circuit comprising a critical path;
• a plurality of scan chains, wherein one or more scan chains, of the plurality of scan chains, are coupled to the critical logic circuit and are associated with sensitization of the critical path;
• and
• a control circuit that is coupled to the plurality of scan chains,
• wherein the control circuit is configured to receive one or more configuration datasets, where each configuration dataset comprises a scan chain identifier and a test pattern, and
• wherein for each configuration dataset of the one or more configuration datasets, the control circuit is further configured to (i) identify, from the plurality of scan chains, a scan chain, of the one or more scan chains, that is associated with the scan chain identifier, and (ii) load the identified scan chain with the test pattern to sensitize the critical path.