Scan-shift buffer isolator for dynamic power reduction
AssigneeSTMicroelectronics International N.V.
InventorsAnkur BAL, Aradhana KUMARI
Life of this patent
Estimating the term…
Abstract
An integrated circuit is provided. For example, an integrated circuit comprises a functional data path and a scan-data path. At least a portion of the scan-data path is separate from the functional data path. The portion of the scan-data path which is separate from the functional data path comprises a combined gating/delay element for preventing a scan-data signal from reaching any elements downstream of the combined gating/delay element during a scan mode and for providing some or all of a desired signal delay in the portion of the scan-data path which is separate from the functional data path.
Claims20
An integrated circuit comprising:
- a functional data path;
- and
- a scan-data path, at least a portion of which is separate from the functional data path;
- wherein the portion of the scan-data path which is separate from the functional data path comprises a combined gating/delay element for preventing a scan-data signal from reaching any elements downstream of the combined gating/delay element during a scan mode and for providing some or all of a desired signal delay in the portion of the scan-data path which is separate from the functional data path.
A method comprising:
- inserting a combined gating/delay element into a portion of a scan-data path of an integrated circuit that is separate from a functional data path of the integrated circuit;
- wherein the combined gating/delay element prevents a scan-data signal from reaching any elements downstream of the combined gating/delay element during a scan mode and provides some or all of a desired signal delay in the portion of the scan-data path which is separate from the functional data path.
A computer-implemented method comprising:
- parsing a list of electronic components and electrical connections of an electronic circuit;
- identifying one or more scan flip-flops (SFFs), buffers, and/or inverters in the list of electronic components;
- for each SFF identified in the list of electronic components and electrical connections, tracing a corresponding series of buffers and/or inverters back from a scan input of each corresponding SFF until (a) a flip-flop output or (b) a buffer or inverter with a fanout greater than one is encountered;
- and
- revising the list of electronic components and electrical connections by (a) replacing a foremost buffer or inverter in each series of buffers and/or inverters with a scan-enable (SE)-connected combined gating/delay component, or (b) adding an SE-connected combined gating/delay component immediately preceding the foremost buffer or inverter in each series of buffers and/or inverters.
Dependencies are inferred from the claim text.