US 5,812,561 AGranted

Scan based testing of an integrated circuit for compliance with timing specifications

AssigneeMotorola, Inc.

InventorsGrady L. Giles, Alfred Larry Crouch, Odis Dale Amason, Jr., Matthew Donald Pressly, Clark Gilson Shepard, Michael Alan Mateja, Lee Allen Corley, Daniel T. Marquette, Jason E. Doege

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Abstract

A method and implementation for providing an improved testable design for an integrated circuit (IC) device. The integrated circuit includes a functional path for the implementation of a functional specification as well as a testing path for testing the timing specifications for the integrated circuit. Input switching devices are connected between input terminals of the IC and inputs to sequential circuit elements, for example flip-flop devices, in the IC. Similarly, output switching devices are connected between outputs of the flip-flop devices and output terminals of the IC. The switching devices are selectively operable to alternately connect the flip-flop devices into either a functional IC path for providing functional output signals during functional cycles, or into a testing IC path for providing testing output signals indicative of timing points throughout the IC during testing cycles. The IC is also operable to selectively disable tristate bus drivers during the testing cycles. The switching devices are arranged such that a single output terminal of the IC may be selectively used to provide both functional and testing output signals.

Claims22

Dependent claims

A method for testing timing specifications for an integrated circuit, said integrated circuit having functional circuit paths including sequential circuit elements therein, said functional circuit paths being designed to implement a specified functional specification and provide functional output signals at output terminals of said integrated circuit, said method comprising the steps of:

providing a scan path on said integrated circuit, said scan path being selectively routed on said integrated circuit among selected sequential circuit elements, said scan path being terminated at said integrated circuit output terminals, said integrated circuit input/output terminals also being arranged to selectively provide functional output signals for said functional circuit paths;
applying a first testing signal to said integrated circuit, said first testing signal being operable to effect a testing signal propagation through said scan path and provide a timing output signal at one of said integrated circuit output terminals;
and
applying a second testing signal to said integrated circuit, said second testing signal being applied independently of the first testing signal and independently of the sequential circuit elements, the second testing signal operable to control when the output terminal is used to provide the functional output signals and when the output terminal is used to provide the timing output signal.

1 more element

An integrated circuit comprising:

a plurality of input terminals;
a plurality of output terminals;
logic circuitry connected between said input terminals and said output terminals, said logic circuitry defining a functional circuit path, said logic circuitry including at least one sequential circuit element, said logic circuitry being selectively operable to implement a functional specification for said integrated circuit through a functional circuit path to provide functional output signals at said output terminals;
and
testing signal circuitry connected between said input terminals and said output terminals, said testing signal circuitry defining a testing circuit path, a scan enable signal being applied to said test signal circuitry for controlling shifting of the test data through said testing circuit path, said testing signal circuitry further including a first switching device connecting one of said input terminals to an input terminal of said sequential circuit element, and a second switching device connecting an output terminal of said sequential circuit element to one of said integrated circuit output terminals, said first switching device and said second switching device being controlled by a bus scan enable signal, the bus scan enable signal being applied independently of both the scan enable signal and the at least one sequential circuit element, the bus scan enable signal is operable to control when the plurality of input terminals are used to receive the functional input signals, and to control when the plurality of output terminals are to provide the functional output signals, and to control when the plurality of output terminals are to provide the test data, wherein the use of bus scan enable signal is for implementing a timing analysis of the integrated circuit.

2 more elements

Dependencies are inferred from the claim text.