H10W 90/723
Between laterally-adjacent chips
Official title: {between laterally-adjacent chips}
H10W90/723 (Between laterally-adjacent chips) appears on 57 US grants and 67 published applications in this corpus.
Search patents in H10W- Granted patents
- 57
- Published applications
- 67
- Assignees
- 37
- Inventors
- 192
- Latest grant
- 4 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1996 | 1 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 1 | 0 |
| 2000 | 1 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 1 | 0 |
| 2004 | 0 | 0 |
| 2005 | 1 | 1 |
| 2006 | 0 | 1 |
| 2007 | 0 | 0 |
| 2008 | 0 | 2 |
| 2009 | 1 | 2 |
| 2010 | 0 | 1 |
| 2011 | 1 | 2 |
| 2012 | 3 | 3 |
| 2013 | 4 | 3 |
| 2014 | 3 | 5 |
| 2015 | 9 | 6 |
| 2016 | 5 | 4 |
| 2017 | 3 | 4 |
| 2018 | 3 | 6 |
| 2019 | 4 | 4 |
| 2020 | 7 | 2 |
| 2021 | 2 | 0 |
| 2022 | 0 | 0 |
| 2023 | 0 | 3 |
| 2024 | 0 | 10 |
| 2025 | 3 | 7 |
| 2026 | 4 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
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- Integrated circuit (IC) package employing a metal block with metal interconnects thermally coupling a die to an interposer substrate for dissipating thermal energy of the die, and related fabrication methods21 Apr 2026US 12,610,869 B2QUALCOMM Incorporated
- Interposer device and semiconductor package structure23 Dec 2025US 12,506,057 B2Global Unichip Corporation
- Thermal solutions for artificial intelligence chiplet modules23 Apr 2026US 2026/0114272 A1International Business Machines Corporation
- Semiconductor device and method for manufacturing same30 Oct 2025US 2025/0336871 A1Microchip Technology Incorporated
- Package assembly and method of forming the same10 Jul 2025US 2025/0224556 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor die with buried electrical interconnections26 Jun 2025US 2025/0210463 A1NXP B. V.
- Package architectures having vertically stacked dies and voltage converters19 Jun 2025US 2025/0201766 A1Intel Corporation
Most cited
By later US patents
- Semiconductor device including stacked chips having metal patterned on circuit surface and on edge side of chip56US 5,892,287 ATexas Instruments Incorporated · 1999
- Chip edge interconnect apparatus and method52US 6,611,050 B1International Business Machines Corporation · 2003
- Contact arrangements for stackable microelectronic package structures with multiple ranks33US 9,349,707 B1Invensas Corporation · 2016
- Electronic device and method of manufacturing the same17US 8,354,340 B2Renesas Electronics Corporation · 2013
- Method of manufacturing a semiconductor device16US 5,533,664 AKabushiki Kaisha Toshiba · 1996