Package architectures having vertically stacked dies and voltage converters

A microelectronic assembly, comprising:

• a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, a third surface orthogonal to the first and second surfaces, wherein the first IC die includes a first substrate having first voltage converter (VC) circuitry, a second substrate having compute circuitry, and a metallization stack between the first substrate and the second substrate, wherein interfaces between the first substrate, the metallization stack, and the second substrate are parallel to the first and second surfaces, and wherein the metallization stack includes a conductive trace that is parallel to the first and second surfaces and exposed at the third surface;
• a second IC die including second VC circuitry and having a fourth surface, wherein the third surface of the first IC die is electrically coupled to the fourth surface of the second IC die by a first interconnect;
• and
• a third IC die including memory circuitry, the third IC die having a fifth surface, a sixth surface opposite the fifth surface, a seventh surface orthogonal to the fifth and sixth surfaces, and a conductive trace that is parallel to the fifth and sixth surfaces and exposed at the seventh surface, wherein the seventh surface of the third IC die is electrically coupled to the fourth surface of the second IC die by a second interconnect and the third IC die is electrically coupled to the second VC circuitry in the second IC die.