H10W 46/507
Located in dummy chips or in reference chips
Official title: {Located in dummy chips or in reference chips}
H10W46/507 (Located in dummy chips or in reference chips) appears on 102 US grants and 79 published applications in this corpus.
Search patents in H10W- Granted patents
- 102
- Published applications
- 79
- Assignees
- 62
- Inventors
- 228
- Latest grant
- 24 Jun 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 2 | 0 |
| 1995 | 1 | 0 |
| 1996 | 2 | 0 |
| 1997 | 3 | 0 |
| 1998 | 2 | 0 |
| 1999 | 3 | 0 |
| 2000 | 6 | 0 |
| 2001 | 4 | 1 |
| 2002 | 7 | 2 |
| 2003 | 5 | 5 |
| 2004 | 4 | 7 |
| 2005 | 5 | 10 |
| 2006 | 7 | 8 |
| 2007 | 4 | 7 |
| 2008 | 5 | 1 |
| 2009 | 4 | 8 |
| 2010 | 2 | 3 |
| 2011 | 5 | 2 |
| 2012 | 2 | 1 |
| 2013 | 3 | 4 |
| 2014 | 4 | 2 |
| 2015 | 2 | 2 |
| 2016 | 2 | 0 |
| 2017 | 1 | 0 |
| 2018 | 1 | 0 |
| 2019 | 1 | 3 |
| 2020 | 0 | 1 |
| 2021 | 2 | 3 |
| 2022 | 1 | 3 |
| 2023 | 2 | 3 |
| 2024 | 2 | 1 |
| 2025 | 3 | 1 |
| 2026 | 0 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Dummy patterns in redundant region of double seal ring24 Jun 2025US 12,341,071 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Large die wafer, large die and method of forming the same3 Jun 2025US 12,322,707 B2Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
- Chip package and method for forming a chip package having first and second stack of dummy metal layers surround the sensing region8 Apr 2025US 12,272,712 B2Xintec Inc.
- Template, workpiece, and alignment method3 Sep 2024US 12,078,922 B2Kioxia Corporation
- Semiconductor package structures and methods of manufacturing the same2 Jan 2024US 11,862,585 B2Advanced Semiconductor Engineering, Inc.
- Method for fabricating semiconductor structure7 May 2026US 2026/0130228 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Dummy Patterns in Redundant Region of Double Seal Ring25 Sep 2025US 2025/0300028 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Alignment pattern having an e shape27 Jun 2024US 2024/0213173 A1Micron Technology, Inc.
- Dummy Patterns in Redundant Region of Double Seal Ring16 Nov 2023US 2023/0369148 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Chip package and method for forming the same16 Nov 2023US 2023/0369371 A1Xintec Inc.
Most cited
By later US patents
- Alignment of MTJ stack to conductive lines in the absence of topography273US 7,223,612 B2Infineon Technologies AG · 2007
- Method and system for identifying defects in a semiconductor144US 6,292,582 B12001
- Method for separating circuit dies from a wafer112US 5,362,681 AAnaglog Devices, Inc. · 1994
- Integral semiconductor wafer map recording97US 5,256,578 AMotorola, Inc. · 1993
- Method of fabrication an inverse open frame alignment mark76US 5,401,691 ACypress Semiconductor Corporation · 1995