Dummy Patterns in Redundant Region of Double Seal Ring
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShan-Yu Huang, Hsiao-Wen Chung, Yi-Lun Chen, Huang-Sheng Lin
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Abstract
A semiconductor structure includes first and second inner seal rings each having a first section and a second section substantially perpendicular to the first section. The semiconductor structure further includes an outer seal ring. The outer seal ring has a third section, and a fourth section, and a fifth section. The semiconductor structure further includes dummy patterns substantially uniformly distributed in each of regions between the first inner seal ring and the outer seal ring and between the second inner seal ring and the outer seal ring.
Claims20
A semiconductor structure, comprising:
- a first device region and a second device region;
- a first inner seal ring surrounding a portion of the first device region and a second inner seal ring surrounding a portion of the second device region in a top view;
- an outer seal ring, wherein the first device region, the first inner seal ring, the second device region and the second inner seal ring are encircled by the outer seal ring in the top view;
- a first interconnect line extending from the first device region to the second device region, wherein the first interconnect line is formed on an nth layer of the semiconductor structure, wherein n is greater than 1, wherein the first interconnect line extends through an opening in the first inner seal ring in the nth layer and an opening in the second inner seal ring in the nth layer;
- and
- dummy patterns disposed on a layer of the semiconductor structure, the dummy patterns below the first interconnect line in a cross-sectional view.
A semiconductor structure, comprising:
- a first device region and a second device region;
- a first inner seal ring surrounding a portion of the first device region and a second inner seal ring surrounding a portion of the second device region in a top view;
- an outer seal ring, wherein the first device region, the first inner seal ring, the second device region and the second inner seal ring are encircled by the outer seal ring in the top view;
- a first interconnect line and a second interconnect line each extending from the first device region to the second device region, wherein the first interconnect line and the second interconnect line are formed on an nth layer of the semiconductor structure, wherein n is greater than 1;
- wherein the first interconnect line extends through a first opening in the first inner seal ring in the nth layer and a first opening in the second inner seal ring in the nth layer, wherein the second interconnect line extends through a second opening in the first inner seal ring in the nth layer and a second opening in the second inner seal ring in the nth layer;
- dummy patterns distributed in a region between the first interconnect line and the second interconnect line on the nth layer.
A semiconductor structure, comprising:
- a first seal ring surrounding a portion of a first device region and a second seal ring surrounding a portion of the second device region in a top view;
- a first interconnect line and a second interconnect line each extending from the first device region to the second device region, wherein the first interconnect line and the second interconnect line are formed on an nth metal layer of the semiconductor structure, wherein n is greater than 1, wherein the first interconnect line extends through a first opening in the first seal ring in the nth metal layer and a first opening in the second seal ring in the nth metal layer;
- dummy patterns including a first plurality of features distributed in a region between the first interconnect line and the second interconnect line in the top view, and wherein the dummy patterns extend below the first interconnect line in a cross-sectional view.
Dependencies are inferred from the claim text.