Chip package and method for forming a chip package having first and second stack of dummy metal layers surround the sensing region
AssigneeXintec Inc.
InventorsTsang-Yu Liu, Chaung-Lin Lai, Shu-Ming Chang
Life of this patent
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AssigneeXintec Inc.
InventorsTsang-Yu Liu, Chaung-Lin Lai, Shu-Ming Chang
Estimating the term…
Chip packages and methods for forming the same are provided. The method includes providing a substrate having a chip region and a scribe-line region surrounding the chip region and forming a dielectric layer on an upper surface of the substrate. A dummy structure is formed in the dielectric layer over the scribe-line region of the substrate and extends along edges of the chip region. The dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside. The method also includes performing a sawing process on a portion of the dielectric layer that surrounds the dummy structure, so as to form a saw opening through the dielectric layer. At least the first stack of dummy metal layers remains in the dielectric layer after the sawing process is performed.
A chip package, comprising:
A chip package, comprising:
Dependencies are inferred from the claim text.