Method for fabricating semiconductor structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChien-Hsun LIN
Life of this patent
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Abstract
A method for fabricating a semiconductor structure is provided. The method includes providing a plurality of chip regions on a substrate. The method includes forming a plurality of scribe line regions among the chip regions on the substrate. The scribe line regions each include a testing region having a plurality of testing patterns and a dicing region around the test region. The dicing region has a dummy band adjacent to the testing region, and a plurality of dummy patterns are formed in the dummy band and electrically isolated from the testing patterns. The method also includes separating the chip regions along the dicing region of the scribe line regions.
Claims20
A method for fabricating a semiconductor structure, comprising:
- providing a plurality of chip regions on a substrate;
- forming a plurality of scribe line regions among the chips on the substrate, wherein the scribe line regions each comprise:
- a testing region having a plurality of testing patterns;
- and
- a dicing region around the test region, wherein the dicing region has a dummy band adjacent to the testing region, and a plurality of dummy patterns are formed in the dummy band and electrically isolated from the testing patterns;
- and
- separating the chip regions along the dicing region of the scribe line regions.
A method for fabricating a semiconductor structure, comprising:
- providing a plurality of chip regions on a substrate;
- forming a seal ring around each of the chip regions;
- forming a plurality of scribe line regions among the chip regions on the substrate, wherein the scribe line regions comprise a dicing region around the seal ring, wherein the dicing region has a first dummy band adjacent to the seal ring, and a plurality of first dummy patterns are formed in the first dummy band and electrically isolated from the seal ring;
- and
- separating the chip regions.
A method for fabricating a semiconductor structure, comprising:
- forming an active region, a plurality of channel structures, and a testing device region over a substrate, wherein the channel structures are located between the active region and the testing device region;
- forming a first isolation structure among the channel structures;
- forming a gate structure and an epitaxial structure over the channel structures;
- forming a via contact over the epitaxial structure;
- forming a plurality of dummy patterns over the via contact, wherein the dummy patterns are electrically isolated from the active region and the testing device region, and are grounded through the via contact;
- and
- separating the active region and the testing device region along a blank band of a scribe line region, wherein the blank band is spaced apart from the dummy patterns.
Dependencies are inferred from the claim text.