H10W 20/20
Interconnections within wafers or substrates
Official title: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W20/20 (Interconnections within wafers or substrates) appears on 13,137 US grants and 16,712 published applications in this corpus.
Search patents in H10W- Granted patents
- 13,137
- Published applications
- 16,712
- Assignees
- 1,231
- Inventors
- 15,886
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 19 | 0 |
| 1977 | 6 | 0 |
| 1978 | 6 | 0 |
| 1979 | 2 | 0 |
| 1980 | 9 | 0 |
| 1981 | 2 | 0 |
| 1982 | 4 | 0 |
| 1983 | 11 | 0 |
| 1984 | 3 | 0 |
| 1985 | 8 | 0 |
| 1986 | 6 | 0 |
| 1987 | 3 | 0 |
| 1988 | 8 | 0 |
| 1989 | 10 | 0 |
| 1990 | 10 | 0 |
| 1991 | 16 | 0 |
| 1992 | 13 | 0 |
| 1993 | 10 | 0 |
| 1994 | 15 | 0 |
| 1995 | 20 | 0 |
| 1996 | 12 | 0 |
| 1997 | 12 | 0 |
| 1998 | 19 | 0 |
| 1999 | 22 | 0 |
| 2000 | 28 | 0 |
| 2001 | 46 | 20 |
| 2002 | 64 | 77 |
| 2003 | 71 | 84 |
| 2004 | 82 | 132 |
| 2005 | 88 | 166 |
| 2006 | 126 | 212 |
| 2007 | 89 | 207 |
| 2008 | 116 | 231 |
| 2009 | 163 | 332 |
| 2010 | 224 | 431 |
| 2011 | 329 | 520 |
| 2012 | 383 | 621 |
| 2013 | 580 | 647 |
| 2014 | 669 | 778 |
| 2015 | 744 | 887 |
| 2016 | 923 | 795 |
| 2017 | 900 | 933 |
| 2018 | 857 | 790 |
| 2019 | 800 | 835 |
| 2020 | 804 | 963 |
| 2021 | 780 | 966 |
| 2022 | 743 | 1155 |
| 2023 | 799 | 1320 |
| 2024 | 909 | 1402 |
| 2025 | 924 | 1321 |
| 2026 | 650 | 887 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Integrated circuit package and method of manufacturing the same6 Oct 2026US 12,754,862 B2SK hynix Inc.
- Three-dimensional semiconductor memory device with bridge pattern suppression and electronic system including the same6 Oct 2026US 12,757,398 B2Samsung Electronics Co., Ltd.
- Contact formation with staggered gate patterning6 Oct 2026US 12,757,441 B2International Business Machines Corporation
- Backside power distribution network and signal line integration6 Oct 2026US 12,757,444 B2International Business Machines Corporation
- Staircase structures for accessing three-dimensional memory arrays6 Oct 2026US 12,757,703 B2Micron Technology, Inc.
- Interconnect structure and method of forming same8 Oct 2026US 2026/0306859 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Heterogeneous packaging integration of photonic and electronic elements8 Oct 2026US 2026/0309942 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Memory device with alternating metal lines8 Oct 2026US 2026/0313866 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Integrated chips package structure with capacitor8 Oct 2026US 2026/0313919 A1Taiwan Semiconductor Manufacturing Company.Ltd
- A Multi-Layer Deep-Trench Capacitor8 Oct 2026US 2026/0313925 A1Lotus Microsystems Aps
Most cited
By later US patents
- Three dimensional structure memory1,560US 5,915,167 AElm Technology Corporation · 1999
- Method of fabricating interconnect structure for package-on-package devices1,078US 9,048,222 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- Dummy structure for chip-on-wafer-on-substrate961US 9,425,126 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices775US 7,157,787 B2Intel Corporation · 2007
- Package of integrated circuits and vertical integration749US 6,322,903 B1Tru-Si Technologies, Inc. · 2001