US 12,757,444 B2 · Backside power distribution network and signal line integration

Abstract

A backside power distribution network is provided having an integrated signal line with a backside connection to a transistor gate. In one aspect, a semiconductor device includes: NFETs and PFETs adjacent to one another on a frontside of a wafer; power rails, connected to source/drain regions of the NFETs and PFETs, present on a backside of the wafer in a space between adjacent NFETs and in a space between adjacent PFETs; and a signal line, connected to a gate of the NFETs and PFETs, present on the backside of the wafer in a space between an adjacent NFET and PFET. The NFETs and PFETs can each include a stack of active layers, and gates surrounding at least a portion of each of the active layers in a gate-all-around configuration. A method of fabricating the present semiconductor devices is provided.

Claims15

Dependent claims

A semiconductor device, comprising:

n-channel field-effect transistors (NFETs) and p-channel field-effect transistors (PFETs) adjacent to one another on a frontside of a wafer;
power rails, connected to source/drain regions of the NFETs and the PFETs, present on a backside of the wafer in a space between adjacent NFETs and in a space between adjacent PFETs;
a signal line, connected to a gate of the NFETs and the PFETs, present on the backside of the wafer in a space between an adjacent NFET and PFET;
and
a signal line contact connecting the one of the gates to the signal line, wherein the signal line contact and the gate are integrally formed.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/890,000Filed 17 Aug 2022

Published

US 2024/0063283 A122 Feb 2024

Granted

6 Oct 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 30/6735
Characterised by the shapes, relative sizes or dispositions of the gate electrodes: having gates fully surrounding the channels, e.g. gate-all-around
H10D 62/151
Source or drain regions of field-effect devices: of igfets
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Backside power distribution network and signal line integration

Life of this patent

Backside power distribution network and signal line integration

Life of this patent

Abstract

Claims15