Three-dimensional semiconductor memory device with bridge pattern suppression and electronic system including the same

A three-dimensional semiconductor memory device, comprising:

• a first substrate including a first region, a second region extending from the first region, and a third region extending from the second region;
• a peripheral circuit structure including peripheral circuit transistors on the first substrate;
• a first insulating layer covering the peripheral circuit transistors;
• a second substrate on the peripheral circuit structure;
• lower insulating patterns in the second substrate;
• a stack including interlayer insulating layers and gate electrodes, which are alternately and repeatedly stacked on the second substrate and the lower insulating patterns, and having a staircase structure on the second region;
• a second insulating layer covering the staircase structure of the stack;
• a third insulating layer on the second insulating layer and coplanar with a topmost surface of the stack;
• vertical channel structures on the first region, penetrating the stack, and in contact with the second substrate;
• first contact plugs on the second region, the first contact plugs each penetrating the second and third insulating layers, the stack, and one of the lower insulating patterns, and being electrically connected to the peripheral circuit structure;
• a second contact plug on the third region, penetrating the second insulating layer and the third insulating layer and another of the lower insulating patterns, and being electrically connected to the peripheral circuit structure;
• insulating pads in the third insulating layer and enclosing upper portions of the first contact plugs and the second contact plug, respectively;
• bit lines on the third insulating layer and electrically connected to the vertical channel structures, respectively;
• and
• conductive lines on the third insulating layer and electrically connected to the first contact plugs and the second contact plug, respectively.

An electronic system, comprising:

• a three-dimensional semiconductor memory device;
• and
• a controller electrically connected to the three-dimensional semiconductor memory device and configured to control the three-dimensional semiconductor memory device,
• wherein:
• the three-dimensional semiconductor memory device includes:
• a substrate including a first region, a second region extending from the first region, and a third region extending from the second region;
• a stack including interlayer insulating layers and gate electrodes, which are alternately and repeatedly stacked on the substrate, and having a staircase structure on the second region;
• an insulating layer covering the staircase structure of the stack;
• vertical channel structures on the first region, penetrating the stack, and in contact with the substrate;
• first contact plugs on the second region and penetrating the insulating layer and the stack;
• a second contact plug on the third region and penetrating the insulating layer and the substrate;
• insulating pads in the insulating layer and enclosing upper portions of each of the first and second contact plugs, wherein outer surfaces of the insulating pads are in contact with respective inner surfaces of the insulating layer;
• and
• an input/output pad connected to the second contact plug,
• the controller is electrically connected to the three-dimensional semiconductor memory device through the input/output pad, and
• a height of each of the first contact plugs and the second contact plug in a vertical direction is larger than a height of each of the vertical channel structures in the vertical direction.