Contact formation with staggered gate patterning
AssigneeInternational Business Machines Corporation
InventorsRuilong Xie, Albert M. Chu, Brent A. Anderson, Lawrence A. Clevenger
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a plurality of gate caps over a plurality of gate regions, gate spacers over sidewalls of the plurality of gate regions and the plurality of gate caps, a backside contact under a first source and drain region and a dielectric cap over the first source and drain region. The first source and drain region is located between two adjacent gate regions of the plurality of gate regions.
Claims18
A semiconductor device, the semiconductor device comprising:
- a plurality of gate caps over a plurality of gate regions;
- a plurality of source/drain regions;
- gate spacers over sidewalls of the plurality of gate regions and the plurality of gate caps, wherein the plurality of gate regions is so arranged in a staggered arrangement that there is an overlap region between each two adjacent gate regions of the plurality of gate regions, and the gate spacers pinch off the overlap region;
- a backside contact under a first source/drain region of the plurality of source/drain regions, wherein the first source and drain region is located between two adjacent gate regions of the plurality of gate regions;
- and
- a dielectric cap over the first source and drain region.
A method for forming a semiconductor device, the method comprising:
- forming a plurality of gate caps over a plurality of gate regions;
- forming a plurality of source/drain regions;
- forming gate spacers over sidewalls of the plurality of gate regions and the plurality of gate caps, wherein the plurality of gate regions is so arranged in a staggered arrangement that there is an overlap region between each two adjacent gate regions of the plurality of gate regions. wherein the gate spacers pinch off the overlap region;
- forming a backside contact under a first source/drain region of the plurality of source/drain regions, wherein the first source and drain region is located between two adjacent gate regions of the plurality of gate regions;
- and
- forming a dielectric cap over the first source and drain region.
A semiconductor device, comprising:
- a plurality of nanosheet gates located between a first and second source and drain regions;
- a backside contact under the first source and drain region;
- gate spacers over sidewalls of a gate region of each of the plurality of nanosheet gates, wherein the plurality of nanosheet gates is so arranged in a staggered arrangement that there is an overlap region between each two adjacent nanosheet gates of the plurality of nanosheet gates, and the gate spacers pinch off the overlap region
- a dielectric cap located over the source and drain region, wherein:
- the backside contact is surrounded by a backside interlayer dielectric (BILD), a backside power rail (BSPR), and a backend dielectric isolation (BDI).
Dependencies are inferred from the claim text.